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gerrit-public.fairphone.software / toolchain / llvm-project / 7fab91225715dda965fd09df225345e809762c87 / . / llvm / test / CodeGen / Mips / msa / arithmetic.ll
blob: 303778f7a2167775bb6d1d4ea7329f0e426c7ede [file] [log] [blame]
Daniel Sanders7fab9122013-09-11 12:39:25 +0000[diff] [blame^]1; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
2
3define void @add_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
4 ; CHECK: add_v16i8:
5
6 %1 = load <16 x i8>* %a
7 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
8 %2 = load <16 x i8>* %b
9 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
10 %3 = add <16 x i8> %1, %2
11 ; CHECK-DAG: addv.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
12 store <16 x i8> %3, <16 x i8>* %c
13 ; CHECK-DAG: st.b [[R3]], 0($4)
14
15 ret void
16 ; CHECK: .size add_v16i8
17}
18
19define void @add_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
20 ; CHECK: add_v8i16:
21
22 %1 = load <8 x i16>* %a
23 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
24 %2 = load <8 x i16>* %b
25 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
26 %3 = add <8 x i16> %1, %2
27 ; CHECK-DAG: addv.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
28 store <8 x i16> %3, <8 x i16>* %c
29 ; CHECK-DAG: st.h [[R3]], 0($4)
30
31 ret void
32 ; CHECK: .size add_v8i16
33}
34
35define void @add_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
36 ; CHECK: add_v4i32:
37
38 %1 = load <4 x i32>* %a
39 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
40 %2 = load <4 x i32>* %b
41 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
42 %3 = add <4 x i32> %1, %2
43 ; CHECK-DAG: addv.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
44 store <4 x i32> %3, <4 x i32>* %c
45 ; CHECK-DAG: st.w [[R3]], 0($4)
46
47 ret void
48 ; CHECK: .size add_v4i32
49}
50
51define void @add_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
52 ; CHECK: add_v2i64:
53
54 %1 = load <2 x i64>* %a
55 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
56 %2 = load <2 x i64>* %b
57 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
58 %3 = add <2 x i64> %1, %2
59 ; CHECK-DAG: addv.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
60 store <2 x i64> %3, <2 x i64>* %c
61 ; CHECK-DAG: st.d [[R3]], 0($4)
62
63 ret void
64 ; CHECK: .size add_v2i64
65}
66define void @sub_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
67 ; CHECK: sub_v16i8:
68
69 %1 = load <16 x i8>* %a
70 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
71 %2 = load <16 x i8>* %b
72 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
73 %3 = sub <16 x i8> %1, %2
74 ; CHECK-DAG: subv.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
75 store <16 x i8> %3, <16 x i8>* %c
76 ; CHECK-DAG: st.b [[R3]], 0($4)
77
78 ret void
79 ; CHECK: .size sub_v16i8
80}
81
82define void @sub_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
83 ; CHECK: sub_v8i16:
84
85 %1 = load <8 x i16>* %a
86 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
87 %2 = load <8 x i16>* %b
88 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
89 %3 = sub <8 x i16> %1, %2
90 ; CHECK-DAG: subv.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
91 store <8 x i16> %3, <8 x i16>* %c
92 ; CHECK-DAG: st.h [[R3]], 0($4)
93
94 ret void
95 ; CHECK: .size sub_v8i16
96}
97
98define void @sub_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
99 ; CHECK: sub_v4i32:
100
101 %1 = load <4 x i32>* %a
102 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
103 %2 = load <4 x i32>* %b
104 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
105 %3 = sub <4 x i32> %1, %2
106 ; CHECK-DAG: subv.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
107 store <4 x i32> %3, <4 x i32>* %c
108 ; CHECK-DAG: st.w [[R3]], 0($4)
109
110 ret void
111 ; CHECK: .size sub_v4i32
112}
113
114define void @sub_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
115 ; CHECK: sub_v2i64:
116
117 %1 = load <2 x i64>* %a
118 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
119 %2 = load <2 x i64>* %b
120 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
121 %3 = sub <2 x i64> %1, %2
122 ; CHECK-DAG: subv.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
123 store <2 x i64> %3, <2 x i64>* %c
124 ; CHECK-DAG: st.d [[R3]], 0($4)
125
126 ret void
127 ; CHECK: .size sub_v2i64
128}
129
130define void @mul_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
131 ; CHECK: mul_v16i8:
132
133 %1 = load <16 x i8>* %a
134 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
135 %2 = load <16 x i8>* %b
136 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
137 %3 = mul <16 x i8> %1, %2
138 ; CHECK-DAG: mulv.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
139 store <16 x i8> %3, <16 x i8>* %c
140 ; CHECK-DAG: st.b [[R3]], 0($4)
141
142 ret void
143 ; CHECK: .size mul_v16i8
144}
145
146define void @mul_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
147 ; CHECK: mul_v8i16:
148
149 %1 = load <8 x i16>* %a
150 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
151 %2 = load <8 x i16>* %b
152 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
153 %3 = mul <8 x i16> %1, %2
154 ; CHECK-DAG: mulv.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
155 store <8 x i16> %3, <8 x i16>* %c
156 ; CHECK-DAG: st.h [[R3]], 0($4)
157
158 ret void
159 ; CHECK: .size mul_v8i16
160}
161
162define void @mul_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
163 ; CHECK: mul_v4i32:
164
165 %1 = load <4 x i32>* %a
166 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
167 %2 = load <4 x i32>* %b
168 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
169 %3 = mul <4 x i32> %1, %2
170 ; CHECK-DAG: mulv.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
171 store <4 x i32> %3, <4 x i32>* %c
172 ; CHECK-DAG: st.w [[R3]], 0($4)
173
174 ret void
175 ; CHECK: .size mul_v4i32
176}
177
178define void @mul_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
179 ; CHECK: mul_v2i64:
180
181 %1 = load <2 x i64>* %a
182 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
183 %2 = load <2 x i64>* %b
184 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
185 %3 = mul <2 x i64> %1, %2
186 ; CHECK-DAG: mulv.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
187 store <2 x i64> %3, <2 x i64>* %c
188 ; CHECK-DAG: st.d [[R3]], 0($4)
189
190 ret void
191 ; CHECK: .size mul_v2i64
192}
193
194define void @div_s_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
195 ; CHECK: div_s_v16i8:
196
197 %1 = load <16 x i8>* %a
198 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
199 %2 = load <16 x i8>* %b
200 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
201 %3 = sdiv <16 x i8> %1, %2
202 ; CHECK-DAG: div_s.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
203 store <16 x i8> %3, <16 x i8>* %c
204 ; CHECK-DAG: st.b [[R3]], 0($4)
205
206 ret void
207 ; CHECK: .size div_s_v16i8
208}
209
210define void @div_s_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
211 ; CHECK: div_s_v8i16:
212
213 %1 = load <8 x i16>* %a
214 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
215 %2 = load <8 x i16>* %b
216 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
217 %3 = sdiv <8 x i16> %1, %2
218 ; CHECK-DAG: div_s.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
219 store <8 x i16> %3, <8 x i16>* %c
220 ; CHECK-DAG: st.h [[R3]], 0($4)
221
222 ret void
223 ; CHECK: .size div_s_v8i16
224}
225
226define void @div_s_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
227 ; CHECK: div_s_v4i32:
228
229 %1 = load <4 x i32>* %a
230 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
231 %2 = load <4 x i32>* %b
232 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
233 %3 = sdiv <4 x i32> %1, %2
234 ; CHECK-DAG: div_s.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
235 store <4 x i32> %3, <4 x i32>* %c
236 ; CHECK-DAG: st.w [[R3]], 0($4)
237
238 ret void
239 ; CHECK: .size div_s_v4i32
240}
241
242define void @div_s_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
243 ; CHECK: div_s_v2i64:
244
245 %1 = load <2 x i64>* %a
246 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
247 %2 = load <2 x i64>* %b
248 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
249 %3 = sdiv <2 x i64> %1, %2
250 ; CHECK-DAG: div_s.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
251 store <2 x i64> %3, <2 x i64>* %c
252 ; CHECK-DAG: st.d [[R3]], 0($4)
253
254 ret void
255 ; CHECK: .size div_s_v2i64
256}
257
258define void @div_u_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
259 ; CHECK: div_u_v16i8:
260
261 %1 = load <16 x i8>* %a
262 ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
263 %2 = load <16 x i8>* %b
264 ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
265 %3 = udiv <16 x i8> %1, %2
266 ; CHECK-DAG: div_u.b [[R3:\$w[0-9]+]], [[R1]], [[R2]]
267 store <16 x i8> %3, <16 x i8>* %c
268 ; CHECK-DAG: st.b [[R3]], 0($4)
269
270 ret void
271 ; CHECK: .size div_u_v16i8
272}
273
274define void @div_u_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
275 ; CHECK: div_u_v8i16:
276
277 %1 = load <8 x i16>* %a
278 ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
279 %2 = load <8 x i16>* %b
280 ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
281 %3 = udiv <8 x i16> %1, %2
282 ; CHECK-DAG: div_u.h [[R3:\$w[0-9]+]], [[R1]], [[R2]]
283 store <8 x i16> %3, <8 x i16>* %c
284 ; CHECK-DAG: st.h [[R3]], 0($4)
285
286 ret void
287 ; CHECK: .size div_u_v8i16
288}
289
290define void @div_u_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
291 ; CHECK: div_u_v4i32:
292
293 %1 = load <4 x i32>* %a
294 ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
295 %2 = load <4 x i32>* %b
296 ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
297 %3 = udiv <4 x i32> %1, %2
298 ; CHECK-DAG: div_u.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
299 store <4 x i32> %3, <4 x i32>* %c
300 ; CHECK-DAG: st.w [[R3]], 0($4)
301
302 ret void
303 ; CHECK: .size div_u_v4i32
304}
305
306define void @div_u_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
307 ; CHECK: div_u_v2i64:
308
309 %1 = load <2 x i64>* %a
310 ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
311 %2 = load <2 x i64>* %b
312 ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
313 %3 = udiv <2 x i64> %1, %2
314 ; CHECK-DAG: div_u.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
315 store <2 x i64> %3, <2 x i64>* %c
316 ; CHECK-DAG: st.d [[R3]], 0($4)
317
318 ret void
319 ; CHECK: .size div_u_v2i64
320}