| Ana Pazos | 9d6c553 | 2018-10-04 21:50:54 +0000 | [diff] [blame] | 1 | //===- RISCVSystemOperands.td ----------------------------*- tablegen -*-===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file defines the symbolic operands permitted for various kinds of |
| 11 | // RISC-V system instruction. |
| 12 | // |
| 13 | //===----------------------------------------------------------------------===// |
| 14 | |
| 15 | include "llvm/TableGen/SearchableTable.td" |
| 16 | |
| 17 | //===----------------------------------------------------------------------===// |
| 18 | // CSR (control and status register read/write) instruction options. |
| 19 | //===----------------------------------------------------------------------===// |
| 20 | |
| 21 | class SysReg<string name, bits<12> op> { |
| 22 | string Name = name; |
| 23 | bits<12> Encoding = op; |
| 24 | // FIXME: add these additional fields when needed. |
| 25 | // Privilege Access: Read and Write = 0, 1, 2; Read-Only = 3. |
| 26 | // Privilege Mode: User = 0, System = 1 or Machine = 3. |
| 27 | // bits<2> ReadWrite = op{11 - 10}; |
| 28 | // bits<2> XMode = op{9 - 8}; |
| 29 | // Check Extra field name and what bits 7-6 correspond to. |
| 30 | // bits<2> Extra = op{7 - 6}; |
| 31 | // Register number without the privilege bits. |
| 32 | // bits<6> Number = op{5 - 0}; |
| 33 | code FeaturesRequired = [{ {} }]; |
| 34 | bit isRV32Only = 0; |
| 35 | } |
| 36 | |
| 37 | def SysRegsList : GenericTable { |
| 38 | let FilterClass = "SysReg"; |
| 39 | // FIXME: add "ReadWrite", "Mode", "Extra", "Number" fields when needed. |
| 40 | let Fields = [ "Name", "Encoding", "FeaturesRequired", "isRV32Only" ]; |
| 41 | |
| 42 | let PrimaryKey = [ "Encoding" ]; |
| 43 | let PrimaryKeyName = "lookupSysRegByEncoding"; |
| 44 | } |
| 45 | |
| 46 | def lookupSysRegByName : SearchIndex { |
| 47 | let Table = SysRegsList; |
| 48 | let Key = [ "Name" ]; |
| 49 | } |
| 50 | |
| 51 | // The following CSR encodings match those given in Tables 2.2, |
| 52 | // 2.3, 2.4 and 2.5 in the RISC-V Instruction Set Manual |
| 53 | // Volume II: Privileged Architecture. |
| 54 | |
| 55 | //===-------------------------- |
| 56 | // User Trap Setup |
| 57 | //===-------------------------- |
| 58 | def : SysReg<"ustatus", 0x000>; |
| 59 | def : SysReg<"uie", 0x004>; |
| 60 | def : SysReg<"utvec", 0x005>; |
| 61 | |
| 62 | //===-------------------------- |
| 63 | // User Trap Handling |
| 64 | //===-------------------------- |
| 65 | def : SysReg<"uscratch", 0x040>; |
| 66 | def : SysReg<"uepc", 0x041>; |
| 67 | def : SysReg<"ucause", 0x042>; |
| 68 | def : SysReg<"utval", 0x043>; |
| 69 | def : SysReg<"uip", 0x044>; |
| 70 | |
| 71 | //===-------------------------- |
| 72 | // User Floating-Point CSRs |
| 73 | //===-------------------------- |
| 74 | |
| 75 | let FeaturesRequired = [{ {RISCV::FeatureStdExtF} }] in { |
| 76 | def : SysReg<"fflags", 0x001>; |
| 77 | def : SysReg<"frm", 0x002>; |
| 78 | def : SysReg<"fcsr", 0x003>; |
| 79 | } |
| 80 | |
| 81 | //===-------------------------- |
| 82 | // User Counter/Timers |
| 83 | //===-------------------------- |
| 84 | def : SysReg<"cycle", 0xC00>; |
| 85 | def : SysReg<"time", 0xC01>; |
| 86 | def : SysReg<"instret", 0xC02>; |
| 87 | |
| 88 | def : SysReg<"hpmcounter3", 0xC03>; |
| 89 | def : SysReg<"hpmcounter4", 0xC04>; |
| 90 | def : SysReg<"hpmcounter5", 0xC05>; |
| 91 | def : SysReg<"hpmcounter6", 0xC06>; |
| 92 | def : SysReg<"hpmcounter7", 0xC07>; |
| 93 | def : SysReg<"hpmcounter8", 0xC08>; |
| 94 | def : SysReg<"hpmcounter9", 0xC09>; |
| 95 | def : SysReg<"hpmcounter10", 0xC0A>; |
| 96 | def : SysReg<"hpmcounter11", 0xC0B>; |
| 97 | def : SysReg<"hpmcounter12", 0xC0C>; |
| 98 | def : SysReg<"hpmcounter13", 0xC0D>; |
| 99 | def : SysReg<"hpmcounter14", 0xC0E>; |
| 100 | def : SysReg<"hpmcounter15", 0xC0F>; |
| 101 | def : SysReg<"hpmcounter16", 0xC10>; |
| 102 | def : SysReg<"hpmcounter17", 0xC11>; |
| 103 | def : SysReg<"hpmcounter18", 0xC12>; |
| 104 | def : SysReg<"hpmcounter19", 0xC13>; |
| 105 | def : SysReg<"hpmcounter20", 0xC14>; |
| 106 | def : SysReg<"hpmcounter21", 0xC15>; |
| 107 | def : SysReg<"hpmcounter22", 0xC16>; |
| 108 | def : SysReg<"hpmcounter23", 0xC17>; |
| 109 | def : SysReg<"hpmcounter24", 0xC18>; |
| 110 | def : SysReg<"hpmcounter25", 0xC19>; |
| 111 | def : SysReg<"hpmcounter26", 0xC1A>; |
| 112 | def : SysReg<"hpmcounter27", 0xC1B>; |
| 113 | def : SysReg<"hpmcounter28", 0xC1C>; |
| 114 | def : SysReg<"hpmcounter29", 0xC1D>; |
| 115 | def : SysReg<"hpmcounter30", 0xC1E>; |
| 116 | def : SysReg<"hpmcounter31", 0xC1F>; |
| 117 | |
| 118 | let isRV32Only = 1 in { |
| 119 | def: SysReg<"cycleh", 0xC80>; |
| 120 | def: SysReg<"timeh", 0xC81>; |
| 121 | def: SysReg<"instreth", 0xC82>; |
| 122 | |
| 123 | def: SysReg<"hpmcounter3h", 0xC83>; |
| 124 | def: SysReg<"hpmcounter4h", 0xC84>; |
| 125 | def: SysReg<"hpmcounter5h", 0xC85>; |
| 126 | def: SysReg<"hpmcounter6h", 0xC86>; |
| 127 | def: SysReg<"hpmcounter7h", 0xC87>; |
| 128 | def: SysReg<"hpmcounter8h", 0xC88>; |
| 129 | def: SysReg<"hpmcounter9h", 0xC89>; |
| 130 | def: SysReg<"hpmcounter10h", 0xC8A>; |
| 131 | def: SysReg<"hpmcounter11h", 0xC8B>; |
| 132 | def: SysReg<"hpmcounter12h", 0xC8C>; |
| 133 | def: SysReg<"hpmcounter13h", 0xC8D>; |
| 134 | def: SysReg<"hpmcounter14h", 0xC8E>; |
| 135 | def: SysReg<"hpmcounter15h", 0xC8F>; |
| 136 | def: SysReg<"hpmcounter16h", 0xC90>; |
| 137 | def: SysReg<"hpmcounter17h", 0xC91>; |
| 138 | def: SysReg<"hpmcounter18h", 0xC92>; |
| 139 | def: SysReg<"hpmcounter19h", 0xC93>; |
| 140 | def: SysReg<"hpmcounter20h", 0xC94>; |
| 141 | def: SysReg<"hpmcounter21h", 0xC95>; |
| 142 | def: SysReg<"hpmcounter22h", 0xC96>; |
| 143 | def: SysReg<"hpmcounter23h", 0xC97>; |
| 144 | def: SysReg<"hpmcounter24h", 0xC98>; |
| 145 | def: SysReg<"hpmcounter25h", 0xC99>; |
| 146 | def: SysReg<"hpmcounter26h", 0xC9A>; |
| 147 | def: SysReg<"hpmcounter27h", 0xC9B>; |
| 148 | def: SysReg<"hpmcounter28h", 0xC9C>; |
| 149 | def: SysReg<"hpmcounter29h", 0xC9D>; |
| 150 | def: SysReg<"hpmcounter30h", 0xC9E>; |
| 151 | def: SysReg<"hpmcounter31h", 0xC9F>; |
| 152 | } |
| 153 | |
| 154 | //===-------------------------- |
| 155 | // Supervisor Trap Setup |
| 156 | //===-------------------------- |
| 157 | def : SysReg<"sstatus", 0x100>; |
| 158 | def : SysReg<"sedeleg", 0x102>; |
| 159 | def : SysReg<"sideleg", 0x103>; |
| 160 | def : SysReg<"sie", 0x104>; |
| 161 | def : SysReg<"stvec", 0x105>; |
| 162 | def : SysReg<"scounteren", 0x106>; |
| 163 | |
| 164 | //===-------------------------- |
| 165 | // Supervisor Trap Handling |
| 166 | //===-------------------------- |
| 167 | def : SysReg<"sscratch", 0x140>; |
| 168 | def : SysReg<"sepc", 0x141>; |
| 169 | def : SysReg<"scause", 0x142>; |
| 170 | def : SysReg<"stval", 0x143>; |
| 171 | def : SysReg<"sip", 0x144>; |
| 172 | |
| 173 | //===------------------------------------- |
| 174 | // Supervisor Protection and Translation |
| 175 | //===------------------------------------- |
| 176 | def : SysReg<"satp", 0x180>; |
| 177 | |
| 178 | //===----------------------------- |
| 179 | // Machine Information Registers |
| 180 | //===----------------------------- |
| 181 | |
| 182 | def : SysReg<"mvendorid", 0xF11>; |
| 183 | def : SysReg<"marchid", 0xF12>; |
| 184 | def : SysReg<"mimpid", 0xF13>; |
| 185 | def : SysReg<"mhartid", 0xF14>; |
| 186 | |
| 187 | //===----------------------------- |
| 188 | // Machine Trap Setup |
| 189 | //===----------------------------- |
| 190 | def : SysReg<"mstatus", 0x300>; |
| 191 | def : SysReg<"misa", 0x301>; |
| 192 | def : SysReg<"medeleg", 0x302>; |
| 193 | def : SysReg<"mideleg", 0x303>; |
| 194 | def : SysReg<"mie", 0x304>; |
| 195 | def : SysReg<"mtvec", 0x305>; |
| 196 | def : SysReg<"mcounteren", 0x306>; |
| 197 | |
| 198 | //===----------------------------- |
| 199 | // Machine Trap Handling |
| 200 | //===----------------------------- |
| 201 | def : SysReg<"mscratch", 0x340>; |
| 202 | def : SysReg<"mepc", 0x341>; |
| 203 | def : SysReg<"mcause", 0x342>; |
| 204 | def : SysReg<"mtval", 0x343>; |
| 205 | def : SysReg<"mip", 0x344>; |
| 206 | |
| 207 | //===---------------------------------- |
| 208 | // Machine Protection and Translation |
| 209 | //===---------------------------------- |
| 210 | def : SysReg<"pmpcfg0", 0x3A0>; |
| 211 | def : SysReg<"pmpcfg2", 0x3A2>; |
| 212 | let isRV32Only = 1 in { |
| 213 | def : SysReg<"pmpcfg1", 0x3A1>; |
| 214 | def : SysReg<"pmpcfg3", 0x3A3>; |
| 215 | } |
| 216 | |
| 217 | def : SysReg<"pmpaddr0", 0x3B0>; |
| 218 | def : SysReg<"pmpaddr1", 0x3B1>; |
| 219 | def : SysReg<"pmpaddr2", 0x3B2>; |
| 220 | def : SysReg<"pmpaddr3", 0x3B3>; |
| 221 | def : SysReg<"pmpaddr4", 0x3B4>; |
| 222 | def : SysReg<"pmpaddr5", 0x3B5>; |
| 223 | def : SysReg<"pmpaddr6", 0x3B6>; |
| 224 | def : SysReg<"pmpaddr7", 0x3B7>; |
| 225 | def : SysReg<"pmpaddr8", 0x3B8>; |
| 226 | def : SysReg<"pmpaddr9", 0x3B9>; |
| 227 | def : SysReg<"pmpaddr10", 0x3BA>; |
| 228 | def : SysReg<"pmpaddr11", 0x3BB>; |
| 229 | def : SysReg<"pmpaddr12", 0x3BC>; |
| 230 | def : SysReg<"pmpaddr13", 0x3BD>; |
| 231 | def : SysReg<"pmpaddr14", 0x3BE>; |
| 232 | def : SysReg<"pmpaddr15", 0x3BF>; |
| 233 | |
| 234 | |
| 235 | //===-------------------------- |
| 236 | // Machine Counter and Timers |
| 237 | //===-------------------------- |
| 238 | def : SysReg<"mcycle", 0xB00>; |
| 239 | def : SysReg<"minstret", 0xB02>; |
| 240 | |
| 241 | def : SysReg<"mhpmcounter3", 0xB03>; |
| 242 | def : SysReg<"mhpmcounter4", 0xB04>; |
| 243 | def : SysReg<"mhpmcounter5", 0xB05>; |
| 244 | def : SysReg<"mhpmcounter6", 0xB06>; |
| 245 | def : SysReg<"mhpmcounter7", 0xB07>; |
| 246 | def : SysReg<"mhpmcounter8", 0xB08>; |
| 247 | def : SysReg<"mhpmcounter9", 0xB09>; |
| 248 | def : SysReg<"mhpmcounter10", 0xB0A>; |
| 249 | def : SysReg<"mhpmcounter11", 0xB0B>; |
| 250 | def : SysReg<"mhpmcounter12", 0xB0C>; |
| 251 | def : SysReg<"mhpmcounter13", 0xB0D>; |
| 252 | def : SysReg<"mhpmcounter14", 0xB0E>; |
| 253 | def : SysReg<"mhpmcounter15", 0xB0F>; |
| 254 | def : SysReg<"mhpmcounter16", 0xB10>; |
| 255 | def : SysReg<"mhpmcounter17", 0xB11>; |
| 256 | def : SysReg<"mhpmcounter18", 0xB12>; |
| 257 | def : SysReg<"mhpmcounter19", 0xB13>; |
| 258 | def : SysReg<"mhpmcounter20", 0xB14>; |
| 259 | def : SysReg<"mhpmcounter21", 0xB15>; |
| 260 | def : SysReg<"mhpmcounter22", 0xB16>; |
| 261 | def : SysReg<"mhpmcounter23", 0xB17>; |
| 262 | def : SysReg<"mhpmcounter24", 0xB18>; |
| 263 | def : SysReg<"mhpmcounter25", 0xB19>; |
| 264 | def : SysReg<"mhpmcounter26", 0xB1A>; |
| 265 | def : SysReg<"mhpmcounter27", 0xB1B>; |
| 266 | def : SysReg<"mhpmcounter28", 0xB1C>; |
| 267 | def : SysReg<"mhpmcounter29", 0xB1D>; |
| 268 | def : SysReg<"mhpmcounter30", 0xB1E>; |
| 269 | def : SysReg<"mhpmcounter31", 0xB1F>; |
| 270 | |
| 271 | let isRV32Only = 1 in { |
| 272 | def: SysReg<"mcycleh", 0xB80>; |
| 273 | def: SysReg<"minstreth", 0xB82>; |
| 274 | |
| 275 | def: SysReg<"mhpmcounter3h", 0xB83>; |
| 276 | def: SysReg<"mhpmcounter4h", 0xB84>; |
| 277 | def: SysReg<"mhpmcounter5h", 0xB85>; |
| 278 | def: SysReg<"mhpmcounter6h", 0xB86>; |
| 279 | def: SysReg<"mhpmcounter7h", 0xB87>; |
| 280 | def: SysReg<"mhpmcounter8h", 0xB88>; |
| 281 | def: SysReg<"mhpmcounter9h", 0xB89>; |
| 282 | def: SysReg<"mhpmcounter10h", 0xB8A>; |
| 283 | def: SysReg<"mhpmcounter11h", 0xB8B>; |
| 284 | def: SysReg<"mhpmcounter12h", 0xB8C>; |
| 285 | def: SysReg<"mhpmcounter13h", 0xB8D>; |
| 286 | def: SysReg<"mhpmcounter14h", 0xB8E>; |
| 287 | def: SysReg<"mhpmcounter15h", 0xB8F>; |
| 288 | def: SysReg<"mhpmcounter16h", 0xB90>; |
| 289 | def: SysReg<"mhpmcounter17h", 0xB91>; |
| 290 | def: SysReg<"mhpmcounter18h", 0xB92>; |
| 291 | def: SysReg<"mhpmcounter19h", 0xB93>; |
| 292 | def: SysReg<"mhpmcounter20h", 0xB94>; |
| 293 | def: SysReg<"mhpmcounter21h", 0xB95>; |
| 294 | def: SysReg<"mhpmcounter22h", 0xB96>; |
| 295 | def: SysReg<"mhpmcounter23h", 0xB97>; |
| 296 | def: SysReg<"mhpmcounter24h", 0xB98>; |
| 297 | def: SysReg<"mhpmcounter25h", 0xB99>; |
| 298 | def: SysReg<"mhpmcounter26h", 0xB9A>; |
| 299 | def: SysReg<"mhpmcounter27h", 0xB9B>; |
| 300 | def: SysReg<"mhpmcounter28h", 0xB9C>; |
| 301 | def: SysReg<"mhpmcounter29h", 0xB9D>; |
| 302 | def: SysReg<"mhpmcounter30h", 0xB9E>; |
| 303 | def: SysReg<"mhpmcounter31h", 0xB9F>; |
| 304 | } |
| 305 | |
| 306 | //===-------------------------- |
| 307 | // Machine Counter Setup |
| 308 | //===-------------------------- |
| 309 | def : SysReg<"mhpmevent3", 0x323>; |
| 310 | def : SysReg<"mhpmevent4", 0x324>; |
| 311 | def : SysReg<"mhpmevent5", 0x325>; |
| 312 | def : SysReg<"mhpmevent6", 0x326>; |
| 313 | def : SysReg<"mhpmevent7", 0x327>; |
| 314 | def : SysReg<"mhpmevent8", 0x328>; |
| 315 | def : SysReg<"mhpmevent9", 0x329>; |
| 316 | def : SysReg<"mhpmevent10", 0x32A>; |
| 317 | def : SysReg<"mhpmevent11", 0x32B>; |
| 318 | def : SysReg<"mhpmevent12", 0x32C>; |
| 319 | def : SysReg<"mhpmevent13", 0x32D>; |
| 320 | def : SysReg<"mhpmevent14", 0x32E>; |
| 321 | def : SysReg<"mhpmevent15", 0x32F>; |
| 322 | def : SysReg<"mhpmevent16", 0x330>; |
| 323 | def : SysReg<"mhpmevent17", 0x331>; |
| 324 | def : SysReg<"mhpmevent18", 0x332>; |
| 325 | def : SysReg<"mhpmevent19", 0x333>; |
| 326 | def : SysReg<"mhpmevent20", 0x334>; |
| 327 | def : SysReg<"mhpmevent21", 0x335>; |
| 328 | def : SysReg<"mhpmevent22", 0x336>; |
| 329 | def : SysReg<"mhpmevent23", 0x337>; |
| 330 | def : SysReg<"mhpmevent24", 0x338>; |
| 331 | def : SysReg<"mhpmevent25", 0x339>; |
| 332 | def : SysReg<"mhpmevent26", 0x33A>; |
| 333 | def : SysReg<"mhpmevent27", 0x33B>; |
| 334 | def : SysReg<"mhpmevent28", 0x33C>; |
| 335 | def : SysReg<"mhpmevent29", 0x33D>; |
| 336 | def : SysReg<"mhpmevent30", 0x33E>; |
| 337 | def : SysReg<"mhpmevent31", 0x33F>; |
| 338 | |
| 339 | //===----------------------------------------------- |
| 340 | // Debug/ Trace Registers (shared with Debug Mode) |
| 341 | //===----------------------------------------------- |
| 342 | def : SysReg<"tselect", 0x7A0>; |
| 343 | def : SysReg<"tdata1", 0x7A1>; |
| 344 | def : SysReg<"tdata2", 0x7A2>; |
| 345 | def : SysReg<"tdata3", 0x7A3>; |
| 346 | |
| 347 | //===----------------------------------------------- |
| 348 | // Debug Mode Registers |
| 349 | //===----------------------------------------------- |
| 350 | def : SysReg<"dcsr", 0x7B0>; |
| 351 | def : SysReg<"dpc", 0x7B1>; |
| 352 | def : SysReg<"dscratch", 0x7B2>; |