Matt Arsenault | a78ca62 | 2017-02-15 22:17:09 +0000 | [diff] [blame] | 1 | ;RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s |
| 2 | ;RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s |
| 3 | |
| 4 | ; GCN-LABEL: {{^}}test_interrupt: |
| 5 | ; GCN: s_mov_b32 m0, 0 |
| 6 | ; GCN-NOT: s_mov_b32 m0 |
| 7 | ; GCN: s_sendmsg sendmsg(MSG_INTERRUPT) |
Matt Arsenault | 3dbeefa | 2017-03-21 21:39:51 +0000 | [diff] [blame] | 8 | define amdgpu_kernel void @test_interrupt() { |
Matt Arsenault | a78ca62 | 2017-02-15 22:17:09 +0000 | [diff] [blame] | 9 | body: |
| 10 | call void @llvm.amdgcn.s.sendmsg(i32 1, i32 0); |
| 11 | ret void |
| 12 | } |
| 13 | |
| 14 | ; GCN-LABEL: {{^}}test_gs_emit: |
| 15 | ; GCN: s_mov_b32 m0, 0 |
| 16 | ; GCN-NOT: s_mov_b32 m0 |
| 17 | ; GCN: s_sendmsg sendmsg(MSG_GS, GS_OP_EMIT, 0) |
Matt Arsenault | 3dbeefa | 2017-03-21 21:39:51 +0000 | [diff] [blame] | 18 | define amdgpu_kernel void @test_gs_emit() { |
Matt Arsenault | a78ca62 | 2017-02-15 22:17:09 +0000 | [diff] [blame] | 19 | body: |
| 20 | call void @llvm.amdgcn.s.sendmsg(i32 34, i32 0); |
| 21 | ret void |
| 22 | } |
| 23 | |
| 24 | ; GCN-LABEL: {{^}}test_gs_cut: |
| 25 | ; GCN: s_mov_b32 m0, 0 |
| 26 | ; GCN-NOT: s_mov_b32 m0 |
| 27 | ; GCN: s_sendmsg sendmsg(MSG_GS, GS_OP_CUT, 1) |
Matt Arsenault | 3dbeefa | 2017-03-21 21:39:51 +0000 | [diff] [blame] | 28 | define amdgpu_kernel void @test_gs_cut() { |
Matt Arsenault | a78ca62 | 2017-02-15 22:17:09 +0000 | [diff] [blame] | 29 | body: |
| 30 | call void @llvm.amdgcn.s.sendmsg(i32 274, i32 0); |
| 31 | ret void |
| 32 | } |
| 33 | |
| 34 | ; GCN-LABEL: {{^}}test_gs_emit_cut: |
| 35 | ; GCN: s_mov_b32 m0, 0 |
| 36 | ; GCN-NOT: s_mov_b32 m0 |
| 37 | ; GCN: s_sendmsg sendmsg(MSG_GS, GS_OP_EMIT_CUT, 2) |
Matt Arsenault | 3dbeefa | 2017-03-21 21:39:51 +0000 | [diff] [blame] | 38 | define amdgpu_kernel void @test_gs_emit_cut() { |
Matt Arsenault | a78ca62 | 2017-02-15 22:17:09 +0000 | [diff] [blame] | 39 | body: |
| 40 | call void @llvm.amdgcn.s.sendmsg(i32 562, i32 0) |
| 41 | ret void |
| 42 | } |
| 43 | |
| 44 | ; GCN-LABEL: {{^}}test_gs_done: |
| 45 | ; GCN: s_mov_b32 m0, 0 |
| 46 | ; GCN-NOT: s_mov_b32 m0 |
| 47 | ; GCN: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP) |
Matt Arsenault | 3dbeefa | 2017-03-21 21:39:51 +0000 | [diff] [blame] | 48 | define amdgpu_kernel void @test_gs_done() { |
Matt Arsenault | a78ca62 | 2017-02-15 22:17:09 +0000 | [diff] [blame] | 49 | body: |
| 50 | call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0) |
| 51 | ret void |
| 52 | } |
| 53 | |
| 54 | ; GCN-LABEL: {{^}}sendmsg: |
| 55 | ; GCN: s_mov_b32 m0, s0 |
| 56 | ; VI-NEXT: s_nop 0 |
| 57 | ; GCN-NEXT: sendmsg(MSG_GS_DONE, GS_OP_NOP) |
| 58 | ; GCN-NEXT: s_endpgm |
| 59 | define amdgpu_gs void @sendmsg(i32 inreg %a) #0 { |
| 60 | call void @llvm.amdgcn.s.sendmsg(i32 3, i32 %a) |
| 61 | ret void |
| 62 | } |
| 63 | |
| 64 | ; GCN-LABEL: {{^}}sendmsghalt: |
| 65 | ; GCN: s_mov_b32 m0, s0 |
| 66 | ; VI-NEXT: s_nop 0 |
| 67 | ; GCN-NEXT: s_sendmsghalt sendmsg(MSG_INTERRUPT) |
| 68 | ; GCN-NEXT: s_endpgm |
Matt Arsenault | 3dbeefa | 2017-03-21 21:39:51 +0000 | [diff] [blame] | 69 | define amdgpu_kernel void @sendmsghalt(i32 inreg %a) #0 { |
Matt Arsenault | a78ca62 | 2017-02-15 22:17:09 +0000 | [diff] [blame] | 70 | call void @llvm.amdgcn.s.sendmsghalt(i32 1, i32 %a) |
| 71 | ret void |
| 72 | } |
| 73 | |
| 74 | ; GCN-LABEL: {{^}}test_interrupt_halt: |
| 75 | ; GCN: s_mov_b32 m0, 0 |
| 76 | ; GCN-NOT: s_mov_b32 m0 |
| 77 | ; GCN: s_sendmsghalt sendmsg(MSG_INTERRUPT) |
Matt Arsenault | 3dbeefa | 2017-03-21 21:39:51 +0000 | [diff] [blame] | 78 | define amdgpu_kernel void @test_interrupt_halt() { |
Matt Arsenault | a78ca62 | 2017-02-15 22:17:09 +0000 | [diff] [blame] | 79 | body: |
| 80 | call void @llvm.amdgcn.s.sendmsghalt(i32 1, i32 0) |
| 81 | ret void |
| 82 | } |
| 83 | |
| 84 | ; GCN-LABEL: {{^}}test_gs_emit_halt: |
| 85 | ; GCN: s_mov_b32 m0, 0 |
| 86 | ; GCN-NOT: s_mov_b32 m0 |
| 87 | ; GCN: s_sendmsghalt sendmsg(MSG_GS, GS_OP_EMIT, 0) |
Matt Arsenault | 3dbeefa | 2017-03-21 21:39:51 +0000 | [diff] [blame] | 88 | define amdgpu_kernel void @test_gs_emit_halt() { |
Matt Arsenault | a78ca62 | 2017-02-15 22:17:09 +0000 | [diff] [blame] | 89 | body: |
| 90 | call void @llvm.amdgcn.s.sendmsghalt(i32 34, i32 0) |
| 91 | ret void |
| 92 | } |
| 93 | |
| 94 | ; GCN-LABEL: {{^}}test_gs_cut_halt: |
| 95 | ; GCN: s_mov_b32 m0, 0 |
| 96 | ; GCN-NOT: s_mov_b32 m0 |
| 97 | ; GCN: s_sendmsghalt sendmsg(MSG_GS, GS_OP_CUT, 1) |
Matt Arsenault | 3dbeefa | 2017-03-21 21:39:51 +0000 | [diff] [blame] | 98 | define amdgpu_kernel void @test_gs_cut_halt() { |
Matt Arsenault | a78ca62 | 2017-02-15 22:17:09 +0000 | [diff] [blame] | 99 | body: |
| 100 | call void @llvm.amdgcn.s.sendmsghalt(i32 274, i32 0) |
| 101 | ret void |
| 102 | } |
| 103 | |
| 104 | ; GCN-LABEL: {{^}}test_gs_emit_cut_halt: |
| 105 | ; GCN: s_mov_b32 m0, 0 |
| 106 | ; GCN-NOT: s_mov_b32 m0 |
| 107 | ; GCN: s_sendmsghalt sendmsg(MSG_GS, GS_OP_EMIT_CUT, 2) |
Matt Arsenault | 3dbeefa | 2017-03-21 21:39:51 +0000 | [diff] [blame] | 108 | define amdgpu_kernel void @test_gs_emit_cut_halt() { |
Matt Arsenault | a78ca62 | 2017-02-15 22:17:09 +0000 | [diff] [blame] | 109 | body: |
| 110 | call void @llvm.amdgcn.s.sendmsghalt(i32 562, i32 0) |
| 111 | ret void |
| 112 | } |
| 113 | |
| 114 | ; GCN-LABEL: {{^}}test_gs_done_halt: |
| 115 | ; GCN: s_mov_b32 m0, 0 |
| 116 | ; GCN-NOT: s_mov_b32 m0 |
| 117 | ; GCN: s_sendmsghalt sendmsg(MSG_GS_DONE, GS_OP_NOP) |
Matt Arsenault | 3dbeefa | 2017-03-21 21:39:51 +0000 | [diff] [blame] | 118 | define amdgpu_kernel void @test_gs_done_halt() { |
Matt Arsenault | a78ca62 | 2017-02-15 22:17:09 +0000 | [diff] [blame] | 119 | body: |
| 120 | call void @llvm.amdgcn.s.sendmsghalt(i32 3, i32 0) |
| 121 | ret void |
| 122 | } |
| 123 | |
Nicolai Haehnle | 7a87977 | 2018-04-20 07:14:25 +0000 | [diff] [blame] | 124 | ; TODO: This should use s_mul_i32 instead of v_mul_u32_u24 + v_readfirstlane! |
| 125 | ; |
| 126 | ; GCN-LABEL: {{^}}test_mul24: |
| 127 | ; GCN: v_mul_u32_u24_e32 |
| 128 | ; GCN: v_readfirstlane_b32 |
| 129 | ; GCN: s_mov_b32 m0, |
| 130 | ; GCN: s_sendmsg sendmsg(MSG_INTERRUPT) |
| 131 | define amdgpu_gs void @test_mul24(i32 inreg %arg) { |
| 132 | body: |
| 133 | %tmp1 = and i32 %arg, 511 |
| 134 | %tmp2 = mul nuw nsw i32 %tmp1, 12288 |
| 135 | call void @llvm.amdgcn.s.sendmsg(i32 1, i32 %tmp2) |
| 136 | ret void |
| 137 | } |
| 138 | |
Nicolai Haehnle | 7f0d05d | 2018-07-30 09:23:59 +0000 | [diff] [blame] | 139 | ; GCN-LABEL: {{^}}if_sendmsg: |
| 140 | ; GCN: s_cbranch_execz |
| 141 | ; GCN: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP) |
| 142 | define amdgpu_gs void @if_sendmsg(i32 %flag) #0 { |
| 143 | %cc = icmp eq i32 %flag, 0 |
| 144 | br i1 %cc, label %sendmsg, label %end |
| 145 | |
| 146 | sendmsg: |
| 147 | call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0) |
| 148 | br label %end |
| 149 | |
| 150 | end: |
| 151 | ret void |
| 152 | } |
| 153 | |
Matt Arsenault | a78ca62 | 2017-02-15 22:17:09 +0000 | [diff] [blame] | 154 | declare void @llvm.amdgcn.s.sendmsg(i32, i32) #0 |
| 155 | declare void @llvm.amdgcn.s.sendmsghalt(i32, i32) #0 |
Matt Arsenault | a78ca62 | 2017-02-15 22:17:09 +0000 | [diff] [blame] | 156 | |
| 157 | attributes #0 = { nounwind } |