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gerrit-public.fairphone.software / toolchain / llvm-project / 81fe1fbf4abd00b24e078a80cb15a2d2c1343f11 / . / llvm / test / CodeGen / AMDGPU / sext-in-reg-failure-r600.ll
blob: 7ac4e1d9fe4b086b8a59f51a95eb9b7d668a9b63 [file] [log] [blame]
Matt Arsenaultb50eb8d2016-08-31 21:52:27 +0000[diff] [blame]1; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG %s
Matt Arsenault8af47a02016-07-01 22:55:55 +0000[diff] [blame]2;
3; EG-LABEL: {{^}}sext_in_reg_v2i1_in_v2i32_other_amount:
Matt Arsenaultb50eb8d2016-08-31 21:52:27 +0000[diff] [blame]4; EG: MEM_{{.*}} MSKOR [[RES:T[0-9]+]]{{\.[XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]]
Matt Arsenault8af47a02016-07-01 22:55:55 +0000[diff] [blame]5; EG-NOT: BFE
6; EG: ADD_INT
7; EG: LSHL
Matt Arsenaultb50eb8d2016-08-31 21:52:27 +0000[diff] [blame]8; EG: ASHR
Matt Arsenault8af47a02016-07-01 22:55:55 +0000[diff] [blame]9; EG: LSHL
Matt Arsenaultb50eb8d2016-08-31 21:52:27 +0000[diff] [blame]10; EG: ASHR
Matt Arsenault8af47a02016-07-01 22:55:55 +0000[diff] [blame]11; EG: LSHR {{\*?}} [[ADDR]]
12
13; Works with the align 2 removed
Matt Arsenault3dbeefa2017-03-21 21:39:51 +0000[diff] [blame]14define amdgpu_kernel void @sext_in_reg_v2i1_in_v2i32_other_amount(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b) nounwind {
Matt Arsenault8af47a02016-07-01 22:55:55 +0000[diff] [blame]15 %c = add <2 x i32> %a, %b
16 %x = shl <2 x i32> %c, <i32 6, i32 6>
17 %y = ashr <2 x i32> %x, <i32 7, i32 7>
18 store <2 x i32> %y, <2 x i32> addrspace(1)* %out, align 2
19 ret void
20}