blob: eb6007f21c10cbd440290b2e11f2be9460d0773a [file] [log] [blame]
Nicolai Haehnleffbd56a2016-05-05 17:36:36 +00001; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck %s
2; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s
3
4; This used to raise an assertion due to how the choice between uniform and
5; non-uniform branches was determined.
6;
7; CHECK-LABEL: {{^}}main:
8; CHECK: s_cbranch_vccnz
9define amdgpu_ps float @main(<4 x i32> inreg %rsrc) {
10main_body:
11 %v = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 0, i1 true, i1 false)
12 %cc = fcmp une float %v, 1.000000e+00
13 br i1 %cc, label %if, label %else
14
15if:
16 %u = fadd float %v, %v
Matt Arsenault9f5e0ef2017-01-25 04:25:02 +000017 call void asm sideeffect "", ""() #0 ; Prevent ifconversion
Nicolai Haehnleffbd56a2016-05-05 17:36:36 +000018 br label %else
19
20else:
21 %r = phi float [ %v, %main_body ], [ %u, %if ]
22 ret float %r
23}
24
25; Function Attrs: nounwind readonly
26declare float @llvm.amdgcn.buffer.load.f32(<4 x i32>, i32, i32, i1, i1) #0
27
28attributes #0 = { nounwind readonly }