| Krzysztof Parzyszek | 046090d | 2018-03-12 14:01:28 +0000 | [diff] [blame] | 1 | ; RUN: llc -march=hexagon -O2 < %s | FileCheck %s |
| 2 | |
| 3 | ; In DAG combiner, eliminate a store in cases where the store is fed by a |
| 4 | ; load from the same location. This is already done in cases where the store's |
| 5 | ; chain reaches the "output chain" of the load, this tests for cases where |
| 6 | ; the load's "input chain" is reached via an intervening node (eg. TokenFactor) |
| 7 | ; that ensures ordering. |
| 8 | |
| 9 | target triple = "hexagon" |
| 10 | |
| 11 | %s.0 = type { [3 x i32] } |
| 12 | |
| 13 | ; Function Attrs: nounwind |
| 14 | define void @f0(i32 %a0, i32 %a1, %s.0* nocapture %a2, %s.0* nocapture %a3) #0 { |
| 15 | b0: |
| 16 | ; Pick one store that happens as a result. This isn't the best, but a regular |
| 17 | ; expression for a register name matches some unrelated load. |
| 18 | ; CHECK: %bb. |
| 19 | ; CHECK: = memw(r3+#8) |
| 20 | ; CHECK-NOT: memw(r3+#8) = |
| 21 | ; CHECK: %bb. |
| 22 | %v0 = bitcast %s.0* %a2 to i8* |
| 23 | %v1 = bitcast %s.0* %a3 to i8* |
| 24 | call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %v0, i8* align 4 %v1, i32 12, i1 false) |
| 25 | %v2 = bitcast %s.0* %a2 to i96* |
| 26 | %v3 = zext i32 %a0 to i96 |
| 27 | %v4 = load i96, i96* %v2, align 4 |
| 28 | %v5 = shl nuw nsw i96 %v3, 48 |
| 29 | %v6 = and i96 %v5, 281474976710656 |
| 30 | %v7 = and i96 %v4, -281474976710657 |
| 31 | %v8 = or i96 %v7, %v6 |
| 32 | store i96 %v8, i96* %v2, align 4 |
| 33 | %v9 = icmp eq i32 %a1, 2147483647 |
| 34 | br i1 %v9, label %b1, label %b2 |
| 35 | |
| 36 | b1: ; preds = %b0 |
| 37 | %v10 = and i96 %v8, -12582913 |
| 38 | br label %b3 |
| 39 | |
| 40 | b2: ; preds = %b0 |
| 41 | %v11 = bitcast %s.0* %a3 to i96* |
| 42 | %v12 = load i96, i96* %v11, align 4 |
| 43 | %v13 = trunc i96 %v12 to i32 |
| 44 | %v14 = add i32 %v13, %a1 |
| 45 | %v15 = zext i32 %v14 to i96 |
| 46 | %v16 = and i96 %v15, 4194303 |
| 47 | %v17 = and i96 %v8, -4194304 |
| 48 | %v18 = or i96 %v16, %v17 |
| 49 | store i96 %v18, i96* %v2, align 4 |
| 50 | %v19 = load i96, i96* %v11, align 4 |
| 51 | %v20 = and i96 %v19, 12582912 |
| 52 | %v21 = and i96 %v18, -12582913 |
| 53 | %v22 = or i96 %v21, %v20 |
| 54 | br label %b3 |
| 55 | |
| 56 | b3: ; preds = %b2, %b1 |
| 57 | %v23 = phi i96 [ %v22, %b2 ], [ %v10, %b1 ] |
| 58 | store i96 %v23, i96* %v2, align 4 |
| 59 | ret void |
| 60 | } |
| 61 | |
| 62 | ; Function Attrs: argmemonly nounwind |
| 63 | declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture writeonly, i8* nocapture readonly, i32, i1) #1 |
| 64 | |
| 65 | attributes #0 = { nounwind } |
| 66 | attributes #1 = { argmemonly nounwind } |