| Krzysztof Parzyszek | 046090d | 2018-03-12 14:01:28 +0000 | [diff] [blame] | 1 | ; RUN: llc -march=hexagon -enable-pipeliner < %s |
| 2 | ; REQUIRES: asserts |
| 3 | |
| 4 | ; Check that a dead REG_SEQUENCE doesn't ICE. |
| 5 | |
| 6 | ; Function Attrs: nounwind |
| 7 | define void @f0(i32* nocapture %a0, i32 %a1) #0 { |
| 8 | b0: |
| 9 | %v0 = mul nsw i32 %a1, 4 |
| 10 | %v1 = icmp sgt i32 %v0, 0 |
| 11 | br i1 %v1, label %b1, label %b2 |
| 12 | |
| 13 | b1: ; preds = %b1, %b0 |
| 14 | %v2 = phi i32 [ %v11, %b1 ], [ 0, %b0 ] |
| 15 | %v3 = load i32, i32* null, align 4 |
| 16 | %v4 = zext i32 %v3 to i64 |
| 17 | %v5 = getelementptr inbounds i32, i32* %a0, i32 0 |
| 18 | %v6 = load i32, i32* %v5, align 4 |
| 19 | %v7 = zext i32 %v6 to i64 |
| 20 | %v8 = shl nuw i64 %v7, 32 |
| 21 | %v9 = or i64 %v8, %v4 |
| 22 | %v10 = tail call i64 @llvm.hexagon.M2.vdmacs.s0(i64 0, i64 %v9, i64 %v9) |
| 23 | %v11 = add nsw i32 %v2, 4 |
| 24 | %v12 = icmp slt i32 %v11, %v0 |
| 25 | br i1 %v12, label %b1, label %b2 |
| 26 | |
| 27 | b2: ; preds = %b1, %b0 |
| 28 | %v13 = phi i64 [ 0, %b0 ], [ %v10, %b1 ] |
| 29 | %v14 = tail call i64 @llvm.hexagon.S2.asr.r.vw(i64 %v13, i32 6) |
| 30 | store i64 %v14, i64* null, align 8 |
| 31 | unreachable |
| 32 | } |
| 33 | |
| 34 | ; Function Attrs: nounwind readnone |
| 35 | declare i64 @llvm.hexagon.M2.vdmacs.s0(i64, i64, i64) #1 |
| 36 | |
| 37 | ; Function Attrs: nounwind readnone |
| 38 | declare i64 @llvm.hexagon.S2.asr.r.vw(i64, i32) #1 |
| 39 | |
| 40 | attributes #0 = { nounwind } |
| 41 | attributes #1 = { nounwind readnone } |