| Krzysztof Parzyszek | 046090d | 2018-03-12 14:01:28 +0000 | [diff] [blame] | 1 | ; RUN: llc -march=hexagon --enable-pipeliner -hexagon-expand-condsets=0 < %s |
| 2 | ; REQUIRES: asserts |
| 3 | |
| 4 | ; Disable expand-condsets because it will assert on undefined registers. |
| 5 | |
| 6 | define void @f0() #0 { |
| 7 | b0: |
| 8 | br i1 undef, label %b1, label %b2 |
| 9 | |
| 10 | b1: ; preds = %b0 |
| 11 | unreachable |
| 12 | |
| 13 | b2: ; preds = %b0 |
| 14 | br i1 undef, label %b3, label %b4 |
| 15 | |
| 16 | b3: ; preds = %b3, %b2 |
| 17 | br i1 undef, label %b4, label %b3 |
| 18 | |
| 19 | b4: ; preds = %b3, %b2 |
| 20 | %v0 = ashr i32 undef, 25 |
| 21 | %v1 = mul nsw i32 %v0, 2 |
| 22 | %v2 = load i8, i8* undef, align 1 |
| 23 | br i1 undef, label %b5, label %b10 |
| 24 | |
| 25 | b5: ; preds = %b4 |
| 26 | br i1 undef, label %b6, label %b9 |
| 27 | |
| 28 | b6: ; preds = %b5 |
| 29 | br label %b7 |
| 30 | |
| 31 | b7: ; preds = %b7, %b6 |
| 32 | br i1 undef, label %b7, label %b8 |
| 33 | |
| 34 | b8: ; preds = %b7 |
| 35 | br i1 undef, label %b10, label %b9 |
| 36 | |
| 37 | b9: ; preds = %b9, %b8, %b5 |
| 38 | %v3 = phi i8 [ %v7, %b9 ], [ undef, %b8 ], [ %v2, %b5 ] |
| 39 | %v4 = phi i32 [ %v8, %b9 ], [ undef, %b8 ], [ 1, %b5 ] |
| 40 | %v5 = add i32 %v4, undef |
| 41 | %v6 = load i8, i8* undef, align 1 |
| 42 | %v7 = select i1 undef, i8 %v6, i8 %v3 |
| 43 | %v8 = add nsw i32 %v4, 1 |
| 44 | %v9 = icmp eq i32 %v8, %v1 |
| 45 | br i1 %v9, label %b10, label %b9 |
| 46 | |
| 47 | b10: ; preds = %b9, %b8, %b4 |
| 48 | %v10 = phi i8 [ %v2, %b4 ], [ undef, %b8 ], [ %v7, %b9 ] |
| 49 | br i1 false, label %b11, label %b12 |
| 50 | |
| 51 | b11: ; preds = %b10 |
| 52 | unreachable |
| 53 | |
| 54 | b12: ; preds = %b10 |
| 55 | br label %b13 |
| 56 | |
| 57 | b13: ; preds = %b13, %b12 |
| 58 | br label %b13 |
| 59 | } |
| 60 | |
| 61 | attributes #0 = { nounwind "target-cpu"="hexagonv55" } |