| Krzysztof Parzyszek | 3a0a15a | 2018-03-26 15:58:16 +0000 | [diff] [blame] | 1 | ; RUN: llc -march=hexagon -hexagon-bit=false < %s |
| 2 | ; REQUIRES: asserts |
| 3 | |
| 4 | ; Fix for an undefined virtual register assert that was caused by an |
| 5 | ; incorrect phi generated by the pipeliner. In this case, there is a |
| 6 | ; phi that defines a value used by another phi in the next iteration. |
| 7 | ; The pipeliner code for generating new phis was assuming that the |
| 8 | ; definition is processed before the use, so an incorrect value was |
| 9 | ; used. |
| 10 | |
| 11 | ; Function Attrs: nounwind |
| 12 | define void @f0() local_unnamed_addr #0 { |
| 13 | b0: |
| 14 | br label %b1 |
| 15 | |
| 16 | b1: ; preds = %b1, %b0 |
| 17 | %v0 = phi i64 [ 0, %b0 ], [ %v5, %b1 ] |
| 18 | %v1 = phi i64 [ undef, %b0 ], [ %v9, %b1 ] |
| 19 | %v2 = phi i32 [ 0, %b0 ], [ %v10, %b1 ] |
| 20 | %v3 = phi i32 [ undef, %b0 ], [ %v4, %b1 ] |
| 21 | %v4 = phi i32 [ undef, %b0 ], [ %v8, %b1 ] |
| 22 | %v5 = tail call i64 @llvm.hexagon.M2.vdmacs.s0(i64 %v0, i64 %v1, i64 undef) |
| 23 | %v6 = tail call i64 @llvm.hexagon.A2.combinew(i32 %v3, i32 %v3) |
| 24 | %v7 = tail call i64 @llvm.hexagon.M2.vdmacs.s0(i64 undef, i64 %v6, i64 undef) |
| 25 | %v8 = tail call i32 @llvm.hexagon.A2.combine.ll(i32 undef, i32 undef) |
| 26 | %v9 = tail call i64 @llvm.hexagon.A2.combinew(i32 %v8, i32 %v4) |
| 27 | %v10 = add nuw nsw i32 %v2, 1 |
| 28 | %v11 = icmp eq i32 %v10, undef |
| 29 | br i1 %v11, label %b2, label %b1 |
| 30 | |
| 31 | b2: ; preds = %b1 |
| 32 | %v12 = lshr i64 %v7, 32 |
| 33 | %v13 = trunc i64 %v12 to i32 |
| 34 | store i32 %v13, i32* undef, align 4 |
| 35 | %v14 = lshr i64 %v5, 32 |
| 36 | ret void |
| 37 | } |
| 38 | |
| 39 | declare i32 @llvm.hexagon.A2.combine.ll(i32, i32) #1 |
| 40 | declare i64 @llvm.hexagon.A2.combinew(i32, i32) #1 |
| 41 | declare i64 @llvm.hexagon.M2.vdmacs.s0(i64, i64, i64) #1 |
| 42 | |
| 43 | attributes #0 = { nounwind "target-cpu"="hexagonv65" } |
| 44 | attributes #1 = { nounwind readnone } |