| Krzysztof Parzyszek | 046090d | 2018-03-12 14:01:28 +0000 | [diff] [blame] | 1 | ; RUN: llc -march=hexagon < %s | FileCheck %s |
| 2 | |
| 3 | target triple = "hexagon" |
| 4 | |
| 5 | ; CHECK-LABEL: f0: |
| 6 | ; CHECK: r{{[0-9]+}} = cmpyiwh(r{{[0-9]}}:{{[0-9]}},r{{[0-9]+}}*):<<1:rnd:sat |
| 7 | define i32 @f0(double %a0) { |
| 8 | b0: |
| 9 | %v0 = alloca i8, align 1 |
| 10 | %v1 = fptosi double %a0 to i64 |
| 11 | %v2 = tail call i32 @llvm.hexagon.M4.cmpyi.whc(i64 %v1, i32 512) |
| 12 | %v3 = trunc i32 %v2 to i8 |
| 13 | store volatile i8 %v3, i8* %v0, align 1 |
| 14 | %v4 = load volatile i8, i8* %v0, align 1 |
| 15 | %v5 = zext i8 %v4 to i32 |
| 16 | ret i32 %v5 |
| 17 | } |
| 18 | |
| 19 | ; Function Attrs: nounwind readnone |
| 20 | declare i32 @llvm.hexagon.M4.cmpyi.whc(i64, i32) #0 |
| 21 | |
| 22 | ; CHECK-LABEL: f1: |
| 23 | ; CHECK: r{{[0-9]+}} = cmpyrwh(r{{[0-9]}}:{{[0-9]}},r{{[0-9]+}}*):<<1:rnd:sat |
| 24 | define i32 @f1(double %a0) { |
| 25 | b0: |
| 26 | %v0 = alloca i8, align 1 |
| 27 | %v1 = fptosi double %a0 to i64 |
| 28 | %v2 = tail call i32 @llvm.hexagon.M4.cmpyr.whc(i64 %v1, i32 512) |
| 29 | %v3 = trunc i32 %v2 to i8 |
| 30 | store volatile i8 %v3, i8* %v0, align 1 |
| 31 | %v4 = load volatile i8, i8* %v0, align 1 |
| 32 | %v5 = zext i8 %v4 to i32 |
| 33 | ret i32 %v5 |
| 34 | } |
| 35 | |
| 36 | ; Function Attrs: nounwind readnone |
| 37 | declare i32 @llvm.hexagon.M4.cmpyr.whc(i64, i32) #0 |
| 38 | |
| 39 | ; CHECK-LABEL: f2: |
| 40 | ; CHECK: r{{[0-9]+}} = popcount(r{{[0-9]}}:{{[0-9]}}) |
| 41 | define i32 @f2(double %a0) { |
| 42 | b0: |
| 43 | %v0 = alloca i8, align 1 |
| 44 | %v1 = fptosi double %a0 to i64 |
| 45 | %v2 = tail call i32 @llvm.hexagon.S5.popcountp(i64 %v1) |
| 46 | %v3 = trunc i32 %v2 to i8 |
| 47 | store volatile i8 %v3, i8* %v0, align 1 |
| 48 | %v4 = load volatile i8, i8* %v0, align 1 |
| 49 | %v5 = zext i8 %v4 to i32 |
| 50 | ret i32 %v5 |
| 51 | } |
| 52 | |
| 53 | ; Function Attrs: nounwind readnone |
| 54 | declare i32 @llvm.hexagon.S5.popcountp(i64) #0 |
| 55 | |
| 56 | ; CHECK-LABEL: f3: |
| 57 | ; CHECK: p{{[0-3]+}} = sfclass(r{{[0-9]}},#3) |
| 58 | define i32 @f3(float %a0) { |
| 59 | b0: |
| 60 | %v0 = alloca i8, align 1 |
| 61 | %v1 = tail call i32 @llvm.hexagon.F2.sfclass(float %a0, i32 3) |
| 62 | %v2 = trunc i32 %v1 to i8 |
| 63 | store volatile i8 %v2, i8* %v0, align 1 |
| 64 | %v3 = load volatile i8, i8* %v0, align 1 |
| 65 | %v4 = zext i8 %v3 to i32 |
| 66 | ret i32 %v4 |
| 67 | } |
| 68 | |
| 69 | ; Function Attrs: readnone |
| 70 | declare i32 @llvm.hexagon.F2.sfclass(float, i32) #1 |
| 71 | |
| 72 | ; CHECK-LABEL: f4: |
| 73 | ; CHECK: r{{[0-9]+}} = vasrhub(r{{[0-9]}}:{{[0-9]}},#3):sat |
| 74 | define i32 @f4(float %a0) { |
| 75 | b0: |
| 76 | %v0 = alloca i8, align 1 |
| 77 | %v1 = fptosi float %a0 to i64 |
| 78 | %v2 = tail call i32 @llvm.hexagon.S5.asrhub.sat(i64 %v1, i32 3) |
| 79 | %v3 = trunc i32 %v2 to i8 |
| 80 | store volatile i8 %v3, i8* %v0, align 1 |
| 81 | %v4 = load volatile i8, i8* %v0, align 1 |
| 82 | %v5 = zext i8 %v4 to i32 |
| 83 | ret i32 %v5 |
| 84 | } |
| 85 | |
| 86 | ; Function Attrs: nounwind readnone |
| 87 | declare i32 @llvm.hexagon.S5.asrhub.sat(i64, i32) #0 |
| 88 | |
| 89 | attributes #0 = { nounwind readnone } |
| 90 | attributes #1 = { readnone } |