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gerrit-public.fairphone.software / toolchain / llvm-project / 81fe1fbf4abd00b24e078a80cb15a2d2c1343f11 / . / llvm / test / CodeGen / NVPTX / vec-param-load.ll
blob: bf26e5ff1bdbb0a7f1f6cc8ed42ab00d3c495372 [file] [log] [blame]
Justin Holewinskidff28d22013-07-01 12:59:01 +0000[diff] [blame]1; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
2
3target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
4
Artem Belevich29bbdc12017-02-21 22:56:05 +0000[diff] [blame]5define <16 x float> @test_v16f32(<16 x float> %a) {
6; CHECK-LABEL: test_v16f32(
7; CHECK-DAG: ld.param.v4.f32 {[[V_12_15:(%f[0-9]+[, ]*){4}]]}, [test_v16f32_param_0+48];
8; CHECK-DAG: ld.param.v4.f32 {[[V_8_11:(%f[0-9]+[, ]*){4}]]}, [test_v16f32_param_0+32];
9; CHECK-DAG: ld.param.v4.f32 {[[V_4_7:(%f[0-9]+[, ]*){4}]]}, [test_v16f32_param_0+16];
10; CHECK-DAG: ld.param.v4.f32 {[[V_0_3:(%f[0-9]+[, ]*){4}]]}, [test_v16f32_param_0];
11; CHECK-DAG: st.param.v4.f32 [func_retval0+0], {[[V_0_3]]}
12; CHECK-DAG: st.param.v4.f32 [func_retval0+16], {[[V_4_7]]}
13; CHECK-DAG: st.param.v4.f32 [func_retval0+32], {[[V_8_11]]}
14; CHECK-DAG: st.param.v4.f32 [func_retval0+48], {[[V_12_15]]}
15; CHECK: ret;
Justin Holewinskidff28d22013-07-01 12:59:01 +0000[diff] [blame]16 ret <16 x float> %a
17}
Artem Belevich29bbdc12017-02-21 22:56:05 +0000[diff] [blame]18
19define <8 x float> @test_v8f32(<8 x float> %a) {
20; CHECK-LABEL: test_v8f32(
21; CHECK-DAG: ld.param.v4.f32 {[[V_4_7:(%f[0-9]+[, ]*){4}]]}, [test_v8f32_param_0+16];
22; CHECK-DAG: ld.param.v4.f32 {[[V_0_3:(%f[0-9]+[, ]*){4}]]}, [test_v8f32_param_0];
23; CHECK-DAG: st.param.v4.f32 [func_retval0+0], {[[V_0_3]]}
24; CHECK-DAG: st.param.v4.f32 [func_retval0+16], {[[V_4_7]]}
25; CHECK: ret;
26 ret <8 x float> %a
27}
28
29define <4 x float> @test_v4f32(<4 x float> %a) {
30; CHECK-LABEL: test_v4f32(
31; CHECK-DAG: ld.param.v4.f32 {[[V_0_3:(%f[0-9]+[, ]*){4}]]}, [test_v4f32_param_0];
32; CHECK-DAG: st.param.v4.f32 [func_retval0+0], {[[V_0_3]]}
33; CHECK: ret;
34 ret <4 x float> %a
35}
36
37define <2 x float> @test_v2f32(<2 x float> %a) {
38; CHECK-LABEL: test_v2f32(
39; CHECK-DAG: ld.param.v2.f32 {[[V_0_3:(%f[0-9]+[, ]*){2}]]}, [test_v2f32_param_0];
40; CHECK-DAG: st.param.v2.f32 [func_retval0+0], {[[V_0_3]]}
41; CHECK: ret;
42 ret <2 x float> %a
43}
44
45; Oddly shaped vectors should not load any extra elements.
46define <3 x float> @test_v3f32(<3 x float> %a) {
47; CHECK-LABEL: test_v3f32(
48; CHECK-DAG: ld.param.f32 [[V_2:%f[0-9]+]], [test_v3f32_param_0+8];
49; CHECK-DAG: ld.param.v2.f32 {[[V_0_1:(%f[0-9]+[, ]*){2}]]}, [test_v3f32_param_0];
50; CHECK-DAG: st.param.v2.f32 [func_retval0+0], {[[V_0_1]]}
51; CHECK-DAG: st.param.f32 [func_retval0+8], [[V_2]]
52; CHECK: ret;
53 ret <3 x float> %a
54}
55
56define <8 x i64> @test_v8i64(<8 x i64> %a) {
57; CHECK-LABEL: test_v8i64(
58; CHECK-DAG: ld.param.v2.u64 {[[V_6_7:(%rd[0-9]+[, ]*){2}]]}, [test_v8i64_param_0+48];
59; CHECK-DAG: ld.param.v2.u64 {[[V_4_5:(%rd[0-9]+[, ]*){2}]]}, [test_v8i64_param_0+32];
60; CHECK-DAG: ld.param.v2.u64 {[[V_2_3:(%rd[0-9]+[, ]*){2}]]}, [test_v8i64_param_0+16];
61; CHECK-DAG: ld.param.v2.u64 {[[V_0_1:(%rd[0-9]+[, ]*){2}]]}, [test_v8i64_param_0];
62; CHECK-DAG: st.param.v2.b64 [func_retval0+0], {[[V_0_1]]}
63; CHECK-DAG: st.param.v2.b64 [func_retval0+16], {[[V_2_3]]}
64; CHECK-DAG: st.param.v2.b64 [func_retval0+32], {[[V_4_5]]}
65; CHECK-DAG: st.param.v2.b64 [func_retval0+48], {[[V_6_7]]}
66; CHECK: ret;
67 ret <8 x i64> %a
68}
69
70define <16 x i16> @test_v16i16(<16 x i16> %a) {
71; CHECK-LABEL: test_v16i16(
72; CHECK-DAG: ld.param.v4.u16 {[[V_12_15:(%rs[0-9]+[, ]*){4}]]}, [test_v16i16_param_0+24];
73; CHECK-DAG: ld.param.v4.u16 {[[V_8_11:(%rs[0-9]+[, ]*){4}]]}, [test_v16i16_param_0+16];
74; CHECK-DAG: ld.param.v4.u16 {[[V_4_7:(%rs[0-9]+[, ]*){4}]]}, [test_v16i16_param_0+8];
75; CHECK-DAG: ld.param.v4.u16 {[[V_0_3:(%rs[0-9]+[, ]*){4}]]}, [test_v16i16_param_0];
76; CHECK-DAG: st.param.v4.b16 [func_retval0+0], {[[V_0_3]]}
77; CHECK-DAG: st.param.v4.b16 [func_retval0+8], {[[V_4_7]]}
78; CHECK-DAG: st.param.v4.b16 [func_retval0+16], {[[V_8_11]]}
79; CHECK-DAG: st.param.v4.b16 [func_retval0+24], {[[V_12_15]]}
80; CHECK: ret;
81 ret <16 x i16> %a
82}