| Bill Schmidt | 164350e | 2015-02-27 23:29:57 +0000 | [diff] [blame] | 1 | ; Verify that the .toc section is aligned on an 8-byte boundary. |
| 2 | |
| Ehsan Amiri | a538b0f | 2016-08-03 18:17:35 +0000 | [diff] [blame] | 3 | ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -filetype=obj -o - | llvm-readobj --sections | FileCheck %s |
| Bill Schmidt | 164350e | 2015-02-27 23:29:57 +0000 | [diff] [blame] | 4 | |
| 5 | define void @test(i32* %a) { |
| 6 | entry: |
| 7 | %a.addr = alloca i32*, align 8 |
| 8 | store i32* %a, i32** %a.addr, align 8 |
| 9 | %0 = load i32*, i32** %a.addr, align 8 |
| 10 | %incdec.ptr = getelementptr inbounds i32, i32* %0, i32 1 |
| 11 | store i32* %incdec.ptr, i32** %a.addr, align 8 |
| 12 | %1 = load i32, i32* %0, align 4 |
| 13 | switch i32 %1, label %sw.epilog [ |
| 14 | i32 17, label %sw.bb |
| 15 | i32 13, label %sw.bb1 |
| 16 | i32 11, label %sw.bb2 |
| 17 | i32 7, label %sw.bb3 |
| 18 | i32 5, label %sw.bb4 |
| 19 | i32 3, label %sw.bb5 |
| 20 | i32 2, label %sw.bb6 |
| 21 | ] |
| 22 | |
| 23 | sw.bb: ; preds = %entry |
| 24 | %2 = load i32*, i32** %a.addr, align 8 |
| 25 | store i32 2, i32* %2, align 4 |
| 26 | br label %sw.epilog |
| 27 | |
| 28 | sw.bb1: ; preds = %entry |
| 29 | %3 = load i32*, i32** %a.addr, align 8 |
| 30 | store i32 3, i32* %3, align 4 |
| 31 | br label %sw.epilog |
| 32 | |
| 33 | sw.bb2: ; preds = %entry |
| 34 | %4 = load i32*, i32** %a.addr, align 8 |
| 35 | store i32 5, i32* %4, align 4 |
| 36 | br label %sw.epilog |
| 37 | |
| 38 | sw.bb3: ; preds = %entry |
| 39 | %5 = load i32*, i32** %a.addr, align 8 |
| 40 | store i32 7, i32* %5, align 4 |
| 41 | br label %sw.epilog |
| 42 | |
| 43 | sw.bb4: ; preds = %entry |
| 44 | %6 = load i32*, i32** %a.addr, align 8 |
| 45 | store i32 11, i32* %6, align 4 |
| 46 | br label %sw.epilog |
| 47 | |
| 48 | sw.bb5: ; preds = %entry |
| 49 | %7 = load i32*, i32** %a.addr, align 8 |
| 50 | store i32 13, i32* %7, align 4 |
| 51 | br label %sw.epilog |
| 52 | |
| 53 | sw.bb6: ; preds = %entry |
| 54 | %8 = load i32*, i32** %a.addr, align 8 |
| 55 | store i32 17, i32* %8, align 4 |
| 56 | br label %sw.epilog |
| 57 | |
| 58 | sw.epilog: ; preds = %entry, %sw.bb6, %sw.bb5, %sw.bb4, %sw.bb3, %sw.bb2, %sw.bb1, %sw.bb |
| 59 | ret void |
| 60 | } |
| 61 | |
| 62 | ; CHECK: Name: .toc |
| 63 | ; CHECK: AddressAlignment: 8 |
| 64 | ; CHECK: Name: .rela.toc |
| 65 | |
| 66 | ; This test was generated from the following from PR22711: |
| 67 | |
| 68 | ;void test(int *a) { |
| 69 | ; switch (*a++) { |
| 70 | ; case 17: *a = 2; break; |
| 71 | ; case 13: *a = 3; break; |
| 72 | ; case 11: *a = 5; break; |
| 73 | ; case 7: *a = 7; break; |
| 74 | ; case 5: *a = 11; break; |
| 75 | ; case 3: *a = 13; break; |
| 76 | ; case 2: *a = 17; break; |
| 77 | ; } |
| 78 | ;} |