| Alex Bradbury | ffc435e | 2017-11-21 08:11:03 +0000 | [diff] [blame] | 1 | ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| 2 | ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ |
| 3 | ; RUN: | FileCheck %s -check-prefix=RV32I |
| 4 | |
| 5 | ; Basic shift support is tested as part of ALU.ll. This file ensures that |
| 6 | ; shifts which may not be supported natively are lowered properly. |
| 7 | |
| 8 | define i64 @lshr64(i64 %a, i64 %b) nounwind { |
| 9 | ; RV32I-LABEL: lshr64: |
| Francis Visoiu Mistrih | 25528d6 | 2017-12-04 17:18:51 +0000 | [diff] [blame] | 10 | ; RV32I: # %bb.0: |
| Alex Bradbury | b014e3d | 2017-12-11 12:34:11 +0000 | [diff] [blame] | 11 | ; RV32I-NEXT: addi sp, sp, -16 |
| Alex Bradbury | 660bcce | 2017-12-11 11:53:54 +0000 | [diff] [blame] | 12 | ; RV32I-NEXT: sw ra, 12(sp) |
| Shiva Chen | d58bd8d | 2018-04-25 14:19:12 +0000 | [diff] [blame] | 13 | ; RV32I-NEXT: call __lshrdi3 |
| Alex Bradbury | 660bcce | 2017-12-11 11:53:54 +0000 | [diff] [blame] | 14 | ; RV32I-NEXT: lw ra, 12(sp) |
| Alex Bradbury | b014e3d | 2017-12-11 12:34:11 +0000 | [diff] [blame] | 15 | ; RV32I-NEXT: addi sp, sp, 16 |
| Alex Bradbury | 59136ff | 2017-12-15 09:47:01 +0000 | [diff] [blame] | 16 | ; RV32I-NEXT: ret |
| Alex Bradbury | ffc435e | 2017-11-21 08:11:03 +0000 | [diff] [blame] | 17 | %1 = lshr i64 %a, %b |
| 18 | ret i64 %1 |
| 19 | } |
| 20 | |
| 21 | define i64 @ashr64(i64 %a, i64 %b) nounwind { |
| 22 | ; RV32I-LABEL: ashr64: |
| Francis Visoiu Mistrih | 25528d6 | 2017-12-04 17:18:51 +0000 | [diff] [blame] | 23 | ; RV32I: # %bb.0: |
| Alex Bradbury | b014e3d | 2017-12-11 12:34:11 +0000 | [diff] [blame] | 24 | ; RV32I-NEXT: addi sp, sp, -16 |
| Alex Bradbury | 660bcce | 2017-12-11 11:53:54 +0000 | [diff] [blame] | 25 | ; RV32I-NEXT: sw ra, 12(sp) |
| Shiva Chen | d58bd8d | 2018-04-25 14:19:12 +0000 | [diff] [blame] | 26 | ; RV32I-NEXT: call __ashrdi3 |
| Alex Bradbury | 660bcce | 2017-12-11 11:53:54 +0000 | [diff] [blame] | 27 | ; RV32I-NEXT: lw ra, 12(sp) |
| Alex Bradbury | b014e3d | 2017-12-11 12:34:11 +0000 | [diff] [blame] | 28 | ; RV32I-NEXT: addi sp, sp, 16 |
| Alex Bradbury | 59136ff | 2017-12-15 09:47:01 +0000 | [diff] [blame] | 29 | ; RV32I-NEXT: ret |
| Alex Bradbury | ffc435e | 2017-11-21 08:11:03 +0000 | [diff] [blame] | 30 | %1 = ashr i64 %a, %b |
| 31 | ret i64 %1 |
| 32 | } |
| 33 | |
| 34 | define i64 @shl64(i64 %a, i64 %b) nounwind { |
| 35 | ; RV32I-LABEL: shl64: |
| Francis Visoiu Mistrih | 25528d6 | 2017-12-04 17:18:51 +0000 | [diff] [blame] | 36 | ; RV32I: # %bb.0: |
| Alex Bradbury | b014e3d | 2017-12-11 12:34:11 +0000 | [diff] [blame] | 37 | ; RV32I-NEXT: addi sp, sp, -16 |
| Alex Bradbury | 660bcce | 2017-12-11 11:53:54 +0000 | [diff] [blame] | 38 | ; RV32I-NEXT: sw ra, 12(sp) |
| Shiva Chen | d58bd8d | 2018-04-25 14:19:12 +0000 | [diff] [blame] | 39 | ; RV32I-NEXT: call __ashldi3 |
| Alex Bradbury | 660bcce | 2017-12-11 11:53:54 +0000 | [diff] [blame] | 40 | ; RV32I-NEXT: lw ra, 12(sp) |
| Alex Bradbury | b014e3d | 2017-12-11 12:34:11 +0000 | [diff] [blame] | 41 | ; RV32I-NEXT: addi sp, sp, 16 |
| Alex Bradbury | 59136ff | 2017-12-15 09:47:01 +0000 | [diff] [blame] | 42 | ; RV32I-NEXT: ret |
| Alex Bradbury | ffc435e | 2017-11-21 08:11:03 +0000 | [diff] [blame] | 43 | %1 = shl i64 %a, %b |
| 44 | ret i64 %1 |
| 45 | } |