Alex Bradbury | e74f519 | 2018-04-26 14:00:35 +0000 | [diff] [blame] | 1 | ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| 2 | ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ |
| 3 | ; RUN: | FileCheck %s -check-prefix=RV32I |
| 4 | |
| 5 | ; TODO: lbu and lhu should be selected to avoid the unnecessary masking. |
| 6 | |
| 7 | @bytes = global [5 x i8] zeroinitializer, align 1 |
| 8 | |
| 9 | define i32 @test_zext_i8() { |
| 10 | ; RV32I-LABEL: test_zext_i8: |
| 11 | ; RV32I: # %bb.0: # %entry |
| 12 | ; RV32I-NEXT: lui a0, %hi(bytes) |
Sameer AbuAsal | 1dc0a8f | 2018-05-17 18:14:53 +0000 | [diff] [blame] | 13 | ; RV32I-NEXT: lbu a1, %lo(bytes)(a0) |
| 14 | ; RV32I-NEXT: addi a2, zero, 136 |
| 15 | ; RV32I-NEXT: bne a1, a2, .LBB0_3 |
Alex Bradbury | e74f519 | 2018-04-26 14:00:35 +0000 | [diff] [blame] | 16 | ; RV32I-NEXT: # %bb.1: # %entry |
Sameer AbuAsal | 1dc0a8f | 2018-05-17 18:14:53 +0000 | [diff] [blame] | 17 | ; RV32I-NEXT: addi a0, a0, %lo(bytes) |
| 18 | ; RV32I-NEXT: lbu a0, 1(a0) |
Alex Bradbury | e74f519 | 2018-04-26 14:00:35 +0000 | [diff] [blame] | 19 | ; RV32I-NEXT: addi a1, zero, 7 |
| 20 | ; RV32I-NEXT: bne a0, a1, .LBB0_3 |
| 21 | ; RV32I-NEXT: # %bb.2: # %if.end |
| 22 | ; RV32I-NEXT: mv a0, zero |
| 23 | ; RV32I-NEXT: ret |
| 24 | ; RV32I-NEXT: .LBB0_3: # %if.then |
| 25 | ; RV32I-NEXT: addi a0, zero, 1 |
| 26 | ; RV32I-NEXT: ret |
| 27 | entry: |
| 28 | %0 = load i8, i8* getelementptr inbounds ([5 x i8], [5 x i8]* @bytes, i32 0, i32 0), align 1 |
| 29 | %cmp = icmp eq i8 %0, -120 |
| 30 | %1 = load i8, i8* getelementptr inbounds ([5 x i8], [5 x i8]* @bytes, i32 0, i32 1), align 1 |
| 31 | %cmp3 = icmp eq i8 %1, 7 |
| 32 | %or.cond = and i1 %cmp, %cmp3 |
| 33 | br i1 %or.cond, label %if.end, label %if.then |
| 34 | |
| 35 | if.then: |
| 36 | ret i32 1 |
| 37 | |
| 38 | if.end: |
| 39 | ret i32 0 |
| 40 | } |
| 41 | |
| 42 | @shorts = global [5 x i16] zeroinitializer, align 2 |
| 43 | |
| 44 | define i32 @test_zext_i16() { |
| 45 | ; RV32I-LABEL: test_zext_i16: |
| 46 | ; RV32I: # %bb.0: # %entry |
Sameer AbuAsal | 1dc0a8f | 2018-05-17 18:14:53 +0000 | [diff] [blame] | 47 | ; RV32I-NEXT: lui a0, %hi(shorts) |
| 48 | ; RV32I-NEXT: lui a1, 16 |
| 49 | ; RV32I-NEXT: addi a1, a1, -120 |
| 50 | ; RV32I-NEXT: lhu a2, %lo(shorts)(a0) |
| 51 | ; RV32I-NEXT: bne a2, a1, .LBB1_3 |
Alex Bradbury | e74f519 | 2018-04-26 14:00:35 +0000 | [diff] [blame] | 52 | ; RV32I-NEXT: # %bb.1: # %entry |
Sameer AbuAsal | 1dc0a8f | 2018-05-17 18:14:53 +0000 | [diff] [blame] | 53 | ; RV32I-NEXT: addi a0, a0, %lo(shorts) |
| 54 | ; RV32I-NEXT: lhu a0, 2(a0) |
Alex Bradbury | e74f519 | 2018-04-26 14:00:35 +0000 | [diff] [blame] | 55 | ; RV32I-NEXT: addi a1, zero, 7 |
| 56 | ; RV32I-NEXT: bne a0, a1, .LBB1_3 |
| 57 | ; RV32I-NEXT: # %bb.2: # %if.end |
| 58 | ; RV32I-NEXT: mv a0, zero |
| 59 | ; RV32I-NEXT: ret |
| 60 | ; RV32I-NEXT: .LBB1_3: # %if.then |
| 61 | ; RV32I-NEXT: addi a0, zero, 1 |
| 62 | ; RV32I-NEXT: ret |
| 63 | entry: |
| 64 | %0 = load i16, i16* getelementptr inbounds ([5 x i16], [5 x i16]* @shorts, i32 0, i32 0), align 2 |
| 65 | %cmp = icmp eq i16 %0, -120 |
| 66 | %1 = load i16, i16* getelementptr inbounds ([5 x i16], [5 x i16]* @shorts, i32 0, i32 1), align 2 |
| 67 | %cmp3 = icmp eq i16 %1, 7 |
| 68 | %or.cond = and i1 %cmp, %cmp3 |
| 69 | br i1 %or.cond, label %if.end, label %if.then |
| 70 | |
| 71 | if.then: |
| 72 | ret i32 1 |
| 73 | |
| 74 | if.end: |
| 75 | ret i32 0 |
| 76 | } |