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gerrit-public.fairphone.software / toolchain / llvm-project / 81fe1fbf4abd00b24e078a80cb15a2d2c1343f11 / . / llvm / test / CodeGen / SystemZ / atomicrmw-minmax-01.ll
blob: 69973f799d3da7e6500d061785a0f7f9e7a5cb8c [file] [log] [blame]
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]1; Test 8-bit atomic min/max operations.
2;
Mandeep Singh Grang029a0562016-04-19 23:51:52 +0000[diff] [blame]3; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]4; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1
5; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2
6
7; Check signed minimum.
8; - CHECK is for the main loop.
9; - CHECK-SHIFT1 makes sure that the negated shift count used by the second
10; RLL is set up correctly. The negation is independent of the NILL and L
11; tested in CHECK.
12; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word
13; before being used, and that the low bits are set to 1. This sequence is
14; independent of the other loop prologue instructions.
15define i8 @f1(i8 *%src, i8 %b) {
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]16; CHECK-LABEL: f1:
Matt Arsenaultab2232c2016-04-29 19:53:16 +0000[diff] [blame]17; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
Jonas Paulssonc63ed222017-10-06 13:59:28 +0000[diff] [blame]18; CHECK-DAG: sll %r2, 3
19; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]20; CHECK: [[LOOP:\.[^:]*]]:
Matt Arsenaultab2232c2016-04-29 19:53:16 +0000[diff] [blame]21; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
Richard Sandiford0fb90ab2013-05-28 10:41:11 +0000[diff] [blame]22; CHECK: crjle [[ROT]], %r3, [[KEEP:\..*]]
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]23; CHECK: risbg [[ROT]], %r3, 32, 39, 0
24; CHECK: [[KEEP]]:
25; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
Matt Arsenaultab2232c2016-04-29 19:53:16 +0000[diff] [blame]26; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]])
Richard Sandiford3d768e32013-07-31 12:30:20 +0000[diff] [blame]27; CHECK: jl [[LOOP]]
Matt Arsenaultab2232c2016-04-29 19:53:16 +0000[diff] [blame]28; CHECK: rll %r2, [[OLD]], 8(%r2)
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]29; CHECK: br %r14
30;
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]31; CHECK-SHIFT1-LABEL: f1:
Matt Arsenaultab2232c2016-04-29 19:53:16 +0000[diff] [blame]32; CHECK-SHIFT1: sll %r2, 3
33; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], %r2
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]34; CHECK-SHIFT1: rll
35; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]])
36; CHECK-SHIFT1: rll
37; CHECK-SHIFT1: br %r14
38;
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]39; CHECK-SHIFT2-LABEL: f1:
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]40; CHECK-SHIFT2: sll %r3, 24
41; CHECK-SHIFT2: rll
Richard Sandiford0fb90ab2013-05-28 10:41:11 +0000[diff] [blame]42; CHECK-SHIFT2: crjle {{%r[0-9]+}}, %r3
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]43; CHECK-SHIFT2: rll
44; CHECK-SHIFT2: rll
45; CHECK-SHIFT2: br %r14
46 %res = atomicrmw min i8 *%src, i8 %b seq_cst
47 ret i8 %res
48}
49
50; Check signed maximum.
51define i8 @f2(i8 *%src, i8 %b) {
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]52; CHECK-LABEL: f2:
Matt Arsenaultab2232c2016-04-29 19:53:16 +0000[diff] [blame]53; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
Jonas Paulssonc63ed222017-10-06 13:59:28 +0000[diff] [blame]54; CHECK-DAG: sll %r2, 3
55; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]56; CHECK: [[LOOP:\.[^:]*]]:
Matt Arsenaultab2232c2016-04-29 19:53:16 +0000[diff] [blame]57; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
Richard Sandiford0fb90ab2013-05-28 10:41:11 +0000[diff] [blame]58; CHECK: crjhe [[ROT]], %r3, [[KEEP:\..*]]
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]59; CHECK: risbg [[ROT]], %r3, 32, 39, 0
60; CHECK: [[KEEP]]:
61; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
Matt Arsenaultab2232c2016-04-29 19:53:16 +0000[diff] [blame]62; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]])
Richard Sandiford3d768e32013-07-31 12:30:20 +0000[diff] [blame]63; CHECK: jl [[LOOP]]
Matt Arsenaultab2232c2016-04-29 19:53:16 +0000[diff] [blame]64; CHECK: rll %r2, [[OLD]], 8(%r2)
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]65; CHECK: br %r14
66;
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]67; CHECK-SHIFT1-LABEL: f2:
Matt Arsenaultab2232c2016-04-29 19:53:16 +0000[diff] [blame]68; CHECK-SHIFT1: sll %r2, 3
69; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], %r2
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]70; CHECK-SHIFT1: rll
71; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]])
72; CHECK-SHIFT1: rll
73; CHECK-SHIFT1: br %r14
74;
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]75; CHECK-SHIFT2-LABEL: f2:
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]76; CHECK-SHIFT2: sll %r3, 24
77; CHECK-SHIFT2: rll
Richard Sandiford0fb90ab2013-05-28 10:41:11 +0000[diff] [blame]78; CHECK-SHIFT2: crjhe {{%r[0-9]+}}, %r3
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]79; CHECK-SHIFT2: rll
80; CHECK-SHIFT2: rll
81; CHECK-SHIFT2: br %r14
82 %res = atomicrmw max i8 *%src, i8 %b seq_cst
83 ret i8 %res
84}
85
86; Check unsigned minimum.
87define i8 @f3(i8 *%src, i8 %b) {
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]88; CHECK-LABEL: f3:
Matt Arsenaultab2232c2016-04-29 19:53:16 +0000[diff] [blame]89; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
Jonas Paulssonc63ed222017-10-06 13:59:28 +0000[diff] [blame]90; CHECK-DAG: sll %r2, 3
91; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]92; CHECK: [[LOOP:\.[^:]*]]:
Matt Arsenaultab2232c2016-04-29 19:53:16 +0000[diff] [blame]93; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
Richard Sandiford93183ee2013-09-18 09:56:40 +0000[diff] [blame]94; CHECK: clrjle [[ROT]], %r3, [[KEEP:\..*]]
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]95; CHECK: risbg [[ROT]], %r3, 32, 39, 0
96; CHECK: [[KEEP]]:
97; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
Matt Arsenaultab2232c2016-04-29 19:53:16 +0000[diff] [blame]98; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]])
Richard Sandiford3d768e32013-07-31 12:30:20 +0000[diff] [blame]99; CHECK: jl [[LOOP]]
Matt Arsenaultab2232c2016-04-29 19:53:16 +0000[diff] [blame]100; CHECK: rll %r2, [[OLD]], 8(%r2)
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]101; CHECK: br %r14
102;
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]103; CHECK-SHIFT1-LABEL: f3:
Matt Arsenaultab2232c2016-04-29 19:53:16 +0000[diff] [blame]104; CHECK-SHIFT1: sll %r2, 3
105; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], %r2
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]106; CHECK-SHIFT1: rll
107; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]])
108; CHECK-SHIFT1: rll
109; CHECK-SHIFT1: br %r14
110;
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]111; CHECK-SHIFT2-LABEL: f3:
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]112; CHECK-SHIFT2: sll %r3, 24
113; CHECK-SHIFT2: rll
Richard Sandiford93183ee2013-09-18 09:56:40 +0000[diff] [blame]114; CHECK-SHIFT2: clrjle {{%r[0-9]+}}, %r3,
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]115; CHECK-SHIFT2: rll
116; CHECK-SHIFT2: rll
117; CHECK-SHIFT2: br %r14
118 %res = atomicrmw umin i8 *%src, i8 %b seq_cst
119 ret i8 %res
120}
121
122; Check unsigned maximum.
123define i8 @f4(i8 *%src, i8 %b) {
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]124; CHECK-LABEL: f4:
Matt Arsenaultab2232c2016-04-29 19:53:16 +0000[diff] [blame]125; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
Jonas Paulssonc63ed222017-10-06 13:59:28 +0000[diff] [blame]126; CHECK-DAG: sll %r2, 3
127; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]128; CHECK: [[LOOP:\.[^:]*]]:
Matt Arsenaultab2232c2016-04-29 19:53:16 +0000[diff] [blame]129; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
Richard Sandiford93183ee2013-09-18 09:56:40 +0000[diff] [blame]130; CHECK: clrjhe [[ROT]], %r3, [[KEEP:\..*]]
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]131; CHECK: risbg [[ROT]], %r3, 32, 39, 0
132; CHECK: [[KEEP]]:
133; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
Matt Arsenaultab2232c2016-04-29 19:53:16 +0000[diff] [blame]134; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]])
Richard Sandiford3d768e32013-07-31 12:30:20 +0000[diff] [blame]135; CHECK: jl [[LOOP]]
Matt Arsenaultab2232c2016-04-29 19:53:16 +0000[diff] [blame]136; CHECK: rll %r2, [[OLD]], 8(%r2)
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]137; CHECK: br %r14
138;
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]139; CHECK-SHIFT1-LABEL: f4:
Matt Arsenaultab2232c2016-04-29 19:53:16 +0000[diff] [blame]140; CHECK-SHIFT1: sll %r2, 3
141; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], %r2
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]142; CHECK-SHIFT1: rll
143; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]])
144; CHECK-SHIFT1: rll
145; CHECK-SHIFT1: br %r14
146;
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]147; CHECK-SHIFT2-LABEL: f4:
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]148; CHECK-SHIFT2: sll %r3, 24
149; CHECK-SHIFT2: rll
Richard Sandiford93183ee2013-09-18 09:56:40 +0000[diff] [blame]150; CHECK-SHIFT2: clrjhe {{%r[0-9]+}}, %r3,
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]151; CHECK-SHIFT2: rll
152; CHECK-SHIFT2: rll
153; CHECK-SHIFT2: br %r14
154 %res = atomicrmw umax i8 *%src, i8 %b seq_cst
155 ret i8 %res
156}
157
158; Check the lowest useful signed minimum value. We need to load 0x81000000
159; into the source register.
160define i8 @f5(i8 *%src) {
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]161; CHECK-LABEL: f5:
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]162; CHECK: llilh [[SRC2:%r[0-9]+]], 33024
Richard Sandiford0fb90ab2013-05-28 10:41:11 +0000[diff] [blame]163; CHECK: crjle [[ROT:%r[0-9]+]], [[SRC2]]
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]164; CHECK: risbg [[ROT]], [[SRC2]], 32, 39, 0
165; CHECK: br %r14
166;
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]167; CHECK-SHIFT1-LABEL: f5:
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]168; CHECK-SHIFT1: br %r14
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]169; CHECK-SHIFT2-LABEL: f5:
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]170; CHECK-SHIFT2: br %r14
171 %res = atomicrmw min i8 *%src, i8 -127 seq_cst
172 ret i8 %res
173}
174
175; Check the highest useful signed maximum value. We need to load 0x7e000000
176; into the source register.
177define i8 @f6(i8 *%src) {
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]178; CHECK-LABEL: f6:
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]179; CHECK: llilh [[SRC2:%r[0-9]+]], 32256
Richard Sandiford0fb90ab2013-05-28 10:41:11 +0000[diff] [blame]180; CHECK: crjhe [[ROT:%r[0-9]+]], [[SRC2]]
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]181; CHECK: risbg [[ROT]], [[SRC2]], 32, 39, 0
182; CHECK: br %r14
183;
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]184; CHECK-SHIFT1-LABEL: f6:
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]185; CHECK-SHIFT1: br %r14
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]186; CHECK-SHIFT2-LABEL: f6:
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]187; CHECK-SHIFT2: br %r14
188 %res = atomicrmw max i8 *%src, i8 126 seq_cst
189 ret i8 %res
190}
191
192; Check the lowest useful unsigned minimum value. We need to load 0x01000000
193; into the source register.
194define i8 @f7(i8 *%src) {
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]195; CHECK-LABEL: f7:
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]196; CHECK: llilh [[SRC2:%r[0-9]+]], 256
Richard Sandiford93183ee2013-09-18 09:56:40 +0000[diff] [blame]197; CHECK: clrjle [[ROT:%r[0-9]+]], [[SRC2]],
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]198; CHECK: risbg [[ROT]], [[SRC2]], 32, 39, 0
199; CHECK: br %r14
200;
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]201; CHECK-SHIFT1-LABEL: f7:
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]202; CHECK-SHIFT1: br %r14
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]203; CHECK-SHIFT2-LABEL: f7:
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]204; CHECK-SHIFT2: br %r14
205 %res = atomicrmw umin i8 *%src, i8 1 seq_cst
206 ret i8 %res
207}
208
209; Check the highest useful unsigned maximum value. We need to load 0xfe000000
210; into the source register.
211define i8 @f8(i8 *%src) {
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]212; CHECK-LABEL: f8:
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]213; CHECK: llilh [[SRC2:%r[0-9]+]], 65024
Richard Sandiford93183ee2013-09-18 09:56:40 +0000[diff] [blame]214; CHECK: clrjhe [[ROT:%r[0-9]+]], [[SRC2]],
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]215; CHECK: risbg [[ROT]], [[SRC2]], 32, 39, 0
216; CHECK: br %r14
217;
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]218; CHECK-SHIFT1-LABEL: f8:
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]219; CHECK-SHIFT1: br %r14
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]220; CHECK-SHIFT2-LABEL: f8:
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]221; CHECK-SHIFT2: br %r14
222 %res = atomicrmw umax i8 *%src, i8 254 seq_cst
223 ret i8 %res
224}