Simon Pilgrim | 68c0e5a | 2018-10-27 15:00:38 +0000 | [diff] [blame] | 1 | ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
Richard Sandiford | dc6c2c9 | 2014-03-21 10:56:30 +0000 | [diff] [blame] | 2 | ; Test conversion of floating-point values to unsigned i32s (z10 only). |
Ulrich Weigand | 9e3577f | 2013-05-06 16:17:29 +0000 | [diff] [blame] | 3 | ; |
Richard Sandiford | dc6c2c9 | 2014-03-21 10:56:30 +0000 | [diff] [blame] | 4 | ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s |
Ulrich Weigand | 9e3577f | 2013-05-06 16:17:29 +0000 | [diff] [blame] | 5 | |
| 6 | ; z10 doesn't have native support for unsigned fp-to-i32 conversions; |
| 7 | ; they were added in z196 as the Convert to Logical family of instructions. |
| 8 | ; Promoting to i64 doesn't generate an inexact condition for values that are |
| 9 | ; outside the i32 range but in the i64 range, so use the default expansion. |
| 10 | |
| 11 | ; Test f32->i32. |
| 12 | define i32 @f1(float %f) { |
Stephen Lin | d24ab20 | 2013-07-14 06:24:09 +0000 | [diff] [blame] | 13 | ; CHECK-LABEL: f1: |
Simon Pilgrim | 68c0e5a | 2018-10-27 15:00:38 +0000 | [diff] [blame] | 14 | ; CHECK: # %bb.0: |
| 15 | ; CHECK-NEXT: larl %r1, .LCPI0_0 |
| 16 | ; CHECK-NEXT: le %f1, 0(%r1) |
| 17 | ; CHECK-NEXT: cebr %f0, %f1 |
| 18 | ; CHECK-NEXT: jnl .LBB0_2 |
| 19 | ; CHECK-NEXT: # %bb.1: |
| 20 | ; CHECK-NEXT: cfebr %r2, 5, %f0 |
| 21 | ; CHECK-NEXT: br %r14 |
| 22 | ; CHECK-NEXT: .LBB0_2: |
| 23 | ; CHECK-NEXT: sebr %f0, %f1 |
| 24 | ; CHECK-NEXT: cfebr %r2, 5, %f0 |
| 25 | ; CHECK-NEXT: xilf %r2, 2147483648 |
| 26 | ; CHECK-NEXT: br %r14 |
Ulrich Weigand | 9e3577f | 2013-05-06 16:17:29 +0000 | [diff] [blame] | 27 | %conv = fptoui float %f to i32 |
| 28 | ret i32 %conv |
| 29 | } |
| 30 | |
| 31 | ; Test f64->i32. |
| 32 | define i32 @f2(double %f) { |
Stephen Lin | d24ab20 | 2013-07-14 06:24:09 +0000 | [diff] [blame] | 33 | ; CHECK-LABEL: f2: |
Simon Pilgrim | 68c0e5a | 2018-10-27 15:00:38 +0000 | [diff] [blame] | 34 | ; CHECK: # %bb.0: |
| 35 | ; CHECK-NEXT: larl %r1, .LCPI1_0 |
| 36 | ; CHECK-NEXT: ldeb %f1, 0(%r1) |
| 37 | ; CHECK-NEXT: cdbr %f0, %f1 |
| 38 | ; CHECK-NEXT: jnl .LBB1_2 |
| 39 | ; CHECK-NEXT: # %bb.1: |
| 40 | ; CHECK-NEXT: cfdbr %r2, 5, %f0 |
| 41 | ; CHECK-NEXT: br %r14 |
| 42 | ; CHECK-NEXT: .LBB1_2: |
| 43 | ; CHECK-NEXT: sdbr %f0, %f1 |
| 44 | ; CHECK-NEXT: cfdbr %r2, 5, %f0 |
| 45 | ; CHECK-NEXT: xilf %r2, 2147483648 |
| 46 | ; CHECK-NEXT: br %r14 |
Ulrich Weigand | 9e3577f | 2013-05-06 16:17:29 +0000 | [diff] [blame] | 47 | %conv = fptoui double %f to i32 |
| 48 | ret i32 %conv |
| 49 | } |
| 50 | |
| 51 | ; Test f128->i32. |
| 52 | define i32 @f3(fp128 *%src) { |
Stephen Lin | d24ab20 | 2013-07-14 06:24:09 +0000 | [diff] [blame] | 53 | ; CHECK-LABEL: f3: |
Simon Pilgrim | 68c0e5a | 2018-10-27 15:00:38 +0000 | [diff] [blame] | 54 | ; CHECK: # %bb.0: |
| 55 | ; CHECK-NEXT: ld %f0, 0(%r2) |
| 56 | ; CHECK-NEXT: ld %f2, 8(%r2) |
| 57 | ; CHECK-NEXT: larl %r1, .LCPI2_0 |
| 58 | ; CHECK-NEXT: lxeb %f1, 0(%r1) |
| 59 | ; CHECK-NEXT: cxbr %f0, %f1 |
| 60 | ; CHECK-NEXT: jnl .LBB2_2 |
| 61 | ; CHECK-NEXT: # %bb.1: |
| 62 | ; CHECK-NEXT: cfxbr %r2, 5, %f0 |
| 63 | ; CHECK-NEXT: br %r14 |
| 64 | ; CHECK-NEXT: .LBB2_2: |
| 65 | ; CHECK-NEXT: sxbr %f0, %f1 |
| 66 | ; CHECK-NEXT: cfxbr %r2, 5, %f0 |
| 67 | ; CHECK-NEXT: xilf %r2, 2147483648 |
| 68 | ; CHECK-NEXT: br %r14 |
Ulrich Weigand | 9dd23b8 | 2018-07-20 12:12:10 +0000 | [diff] [blame] | 69 | %f = load fp128, fp128 *%src |
Ulrich Weigand | 9e3577f | 2013-05-06 16:17:29 +0000 | [diff] [blame] | 70 | %conv = fptoui fp128 %f to i32 |
| 71 | ret i32 %conv |
| 72 | } |