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gerrit-public.fairphone.software / toolchain / llvm-project / 82111f12fb0d36e329c09022da0f0b48034c6cd3 / . / llvm / test / CodeGen / X86 / vselect.ll
blob: 42cf06a4a049aff89c4ba2c217fdd5f685451152 [file] [log] [blame]
NAKAMURA Takumicf396cf2013-12-28 13:04:29 +0000[diff] [blame]1; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=corei7 -mattr=-sse4.1 < %s | FileCheck %s
Andrea Di Biagio46dcddb2013-12-27 20:20:28 +0000[diff] [blame]2
3; Verify that we don't emit packed vector shifts instructions if the
4; condition used by the vector select is a vector of constants.
5
6
7define <4 x float> @test1(<4 x float> %a, <4 x float> %b) {
8 %1 = select <4 x i1> <i1 true, i1 false, i1 true, i1 false>, <4 x float> %a, <4 x float> %b
9 ret <4 x float> %1
10}
11; CHECK-LABEL: test1
12; CHECK-NOT: psllw
13; CHECK-NOT: psraw
14; CHECK: ret
15
16
17define <4 x float> @test2(<4 x float> %a, <4 x float> %b) {
18 %1 = select <4 x i1> <i1 true, i1 true, i1 false, i1 false>, <4 x float> %a, <4 x float> %b
19 ret <4 x float> %1
20}
21; CHECK-LABEL: test2
22; CHECK-NOT: psllw
23; CHECK-NOT: psraw
24; CHECK: ret
25
26
27define <4 x float> @test3(<4 x float> %a, <4 x float> %b) {
28 %1 = select <4 x i1> <i1 false, i1 false, i1 true, i1 true>, <4 x float> %a, <4 x float> %b
29 ret <4 x float> %1
30}
31; CHECK-LABEL: test3
32; CHECK-NOT: psllw
33; CHECK-NOT: psraw
34; CHECK: ret
35
36
37define <4 x float> @test4(<4 x float> %a, <4 x float> %b) {
38 %1 = select <4 x i1> <i1 false, i1 false, i1 false, i1 false>, <4 x float> %a, <4 x float> %b
39 ret <4 x float> %1
40}
41; CHECK-LABEL: test4
42; CHECK-NOT: psllw
43; CHECK-NOT: psraw
44; CHECK: movaps %xmm1, %xmm0
45; CHECK: ret
46
47
48define <4 x float> @test5(<4 x float> %a, <4 x float> %b) {
49 %1 = select <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x float> %a, <4 x float> %b
50 ret <4 x float> %1
51}
52; CHECK-LABEL: test5
53; CHECK-NOT: psllw
54; CHECK-NOT: psraw
55; CHECK: ret
56
57
58define <8 x i16> @test6(<8 x i16> %a, <8 x i16> %b) {
59 %1 = select <8 x i1> <i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false>, <8 x i16> %a, <8 x i16> %a
60 ret <8 x i16> %1
61}
62; CHECK-LABEL: test6
63; CHECK-NOT: psllw
64; CHECK-NOT: psraw
65; CHECK: ret
66
67
68define <8 x i16> @test7(<8 x i16> %a, <8 x i16> %b) {
69 %1 = select <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false>, <8 x i16> %a, <8 x i16> %b
70 ret <8 x i16> %1
71}
72; CHECK-LABEL: test7
73; CHECK-NOT: psllw
74; CHECK-NOT: psraw
75; CHECK: ret
76
77
78define <8 x i16> @test8(<8 x i16> %a, <8 x i16> %b) {
79 %1 = select <8 x i1> <i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true>, <8 x i16> %a, <8 x i16> %b
80 ret <8 x i16> %1
81}
82; CHECK-LABEL: test8
83; CHECK-NOT: psllw
84; CHECK-NOT: psraw
85; CHECK: ret
86
87define <8 x i16> @test9(<8 x i16> %a, <8 x i16> %b) {
88 %1 = select <8 x i1> <i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, <8 x i16> %a, <8 x i16> %b
89 ret <8 x i16> %1
90}
91; CHECK-LABEL: test9
92; CHECK-NOT: psllw
93; CHECK-NOT: psraw
94; CHECK: movaps %xmm1, %xmm0
95; CHECK-NEXT: ret
96
97define <8 x i16> @test10(<8 x i16> %a, <8 x i16> %b) {
98 %1 = select <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i16> %a, <8 x i16> %b
99 ret <8 x i16> %1
100}
101; CHECK-LABEL: test10
102; CHECK-NOT: psllw
103; CHECK-NOT: psraw
104; CHECK: ret
105
106define <8 x i16> @test11(<8 x i16> %a, <8 x i16> %b) {
107 %1 = select <8 x i1> <i1 false, i1 true, i1 true, i1 false, i1 undef, i1 true, i1 true, i1 undef>, <8 x i16> %a, <8 x i16> %b
108 ret <8 x i16> %1
109}
110; CHECK-LABEL: test11
111; CHECK-NOT: psllw
112; CHECK-NOT: psraw
113; CHECK: ret
114
115define <8 x i16> @test12(<8 x i16> %a, <8 x i16> %b) {
116 %1 = select <8 x i1> <i1 false, i1 false, i1 undef, i1 false, i1 false, i1 false, i1 false, i1 undef>, <8 x i16> %a, <8 x i16> %b
117 ret <8 x i16> %1
118}
119; CHECK-LABEL: test12
120; CHECK-NOT: psllw
121; CHECK-NOT: psraw
122; CHECK: ret
123
124define <8 x i16> @test13(<8 x i16> %a, <8 x i16> %b) {
125 %1 = select <8 x i1> <i1 undef, i1 undef, i1 undef, i1 undef, i1 undef, i1 undef, i1 undef, i1 undef>, <8 x i16> %a, <8 x i16> %b
126 ret <8 x i16> %1
127}
128; CHECK-LABEL: test13
129; CHECK-NOT: psllw
130; CHECK-NOT: psraw
131; CHECK: ret
132
Andrea Di Biagio23df4e42014-01-08 18:33:04 +0000[diff] [blame]133; Fold (vselect (build_vector AllOnes), N1, N2) -> N1
134
135define <4 x float> @test14(<4 x float> %a, <4 x float> %b) {
136 %1 = select <4 x i1> <i1 true, i1 undef, i1 true, i1 undef>, <4 x float> %a, <4 x float> %b
137 ret <4 x float> %1
138}
139; CHECK-LABEL: test14
140; CHECK-NOT: psllw
141; CHECK-NOT: psraw
142; CHECK-NOT: pcmpeq
143; CHECK: ret
144
145define <8 x i16> @test15(<8 x i16> %a, <8 x i16> %b) {
146 %1 = select <8 x i1> <i1 true, i1 true, i1 true, i1 undef, i1 undef, i1 true, i1 true, i1 undef>, <8 x i16> %a, <8 x i16> %b
147 ret <8 x i16> %1
148}
149; CHECK-LABEL: test15
150; CHECK-NOT: psllw
151; CHECK-NOT: psraw
152; CHECK-NOT: pcmpeq
153; CHECK: ret
154
155; Fold (vselect (build_vector AllZeros), N1, N2) -> N2
156
157define <4 x float> @test16(<4 x float> %a, <4 x float> %b) {
158 %1 = select <4 x i1> <i1 false, i1 undef, i1 false, i1 undef>, <4 x float> %a, <4 x float> %b
159 ret <4 x float> %1
160}
161; CHECK-LABEL: test16
162; CHECK-NOT: psllw
163; CHECK-NOT: psraw
164; CHECK-NOT: xorps
165; CHECK: ret
166
167define <8 x i16> @test17(<8 x i16> %a, <8 x i16> %b) {
168 %1 = select <8 x i1> <i1 false, i1 false, i1 false, i1 undef, i1 undef, i1 false, i1 false, i1 undef>, <8 x i16> %a, <8 x i16> %b
169 ret <8 x i16> %1
170}
171; CHECK-LABEL: test17
172; CHECK-NOT: psllw
173; CHECK-NOT: psraw
174; CHECK-NOT: xorps
175; CHECK: ret
Andrea Di Biagio46dcddb2013-12-27 20:20:28 +0000[diff] [blame]176
Andrea Di Biagio450d1662014-01-20 19:35:22 +0000[diff] [blame]177define <4 x float> @test18(<4 x float> %a, <4 x float> %b) {
178 %1 = select <4 x i1> <i1 false, i1 true, i1 true, i1 true>, <4 x float> %a, <4 x float> %b
179 ret <4 x float> %1
180}
181; CHECK-LABEL: test18
182; CHECK-NOT: psllw
183; CHECK-NOT: psraw
184; CHECK-NOT: xorps
185; CHECK: movss
186; CHECK: ret
187
188define <4 x i32> @test19(<4 x i32> %a, <4 x i32> %b) {
189 %1 = select <4 x i1> <i1 false, i1 true, i1 true, i1 true>, <4 x i32> %a, <4 x i32> %b
190 ret <4 x i32> %1
191}
192; CHECK-LABEL: test19
193; CHECK-NOT: psllw
194; CHECK-NOT: psraw
195; CHECK-NOT: xorps
196; CHECK: movss
197; CHECK: ret
198
199define <2 x double> @test20(<2 x double> %a, <2 x double> %b) {
200 %1 = select <2 x i1> <i1 false, i1 true>, <2 x double> %a, <2 x double> %b
201 ret <2 x double> %1
202}
203; CHECK-LABEL: test20
204; CHECK-NOT: psllw
205; CHECK-NOT: psraw
206; CHECK-NOT: xorps
207; CHECK: movsd
208; CHECK: ret
209
210define <2 x i64> @test21(<2 x i64> %a, <2 x i64> %b) {
211 %1 = select <2 x i1> <i1 false, i1 true>, <2 x i64> %a, <2 x i64> %b
212 ret <2 x i64> %1
213}
214; CHECK-LABEL: test21
215; CHECK-NOT: psllw
216; CHECK-NOT: psraw
217; CHECK-NOT: xorps
218; CHECK: movsd
219; CHECK: ret
220
221define <4 x float> @test22(<4 x float> %a, <4 x float> %b) {
222 %1 = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x float> %a, <4 x float> %b
223 ret <4 x float> %1
224}
225; CHECK-LABEL: test22
226; CHECK-NOT: psllw
227; CHECK-NOT: psraw
228; CHECK-NOT: xorps
229; CHECK: movss
230; CHECK: ret
231
232define <4 x i32> @test23(<4 x i32> %a, <4 x i32> %b) {
233 %1 = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i32> %a, <4 x i32> %b
234 ret <4 x i32> %1
235}
236; CHECK-LABEL: test23
237; CHECK-NOT: psllw
238; CHECK-NOT: psraw
239; CHECK-NOT: xorps
240; CHECK: movss
241; CHECK: ret
242
243define <2 x double> @test24(<2 x double> %a, <2 x double> %b) {
244 %1 = select <2 x i1> <i1 true, i1 false>, <2 x double> %a, <2 x double> %b
245 ret <2 x double> %1
246}
247; CHECK-LABEL: test24
248; CHECK-NOT: psllw
249; CHECK-NOT: psraw
250; CHECK-NOT: xorps
251; CHECK: movsd
252; CHECK: ret
253
254define <2 x i64> @test25(<2 x i64> %a, <2 x i64> %b) {
255 %1 = select <2 x i1> <i1 true, i1 false>, <2 x i64> %a, <2 x i64> %b
256 ret <2 x i64> %1
257}
258; CHECK-LABEL: test25
259; CHECK-NOT: psllw
260; CHECK-NOT: psraw
261; CHECK-NOT: xorps
262; CHECK: movsd
263; CHECK: ret
264
Filipe Cabecinhas82111f12014-05-30 23:03:11 +0000[diff] [blame^]265define <4 x float> @select_of_shuffles_0(<2 x float> %a0, <2 x float> %b0, <2 x float> %a1, <2 x float> %b1) {
266; CHECK-LABEL: select_of_shuffles_0
267; CHECK-DAG: movlhps %xmm2, [[REGA:%xmm[0-9]+]]
268; CHECK-DAG: movlhps %xmm3, [[REGB:%xmm[0-9]+]]
269; CHECK: subps [[REGB]], [[REGA]]
270 %1 = shufflevector <2 x float> %a0, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
271 %2 = shufflevector <2 x float> %a1, <2 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1>
272 %3 = select <4 x i1> <i1 false, i1 false, i1 true, i1 true>, <4 x float> %2, <4 x float> %1
273 %4 = shufflevector <2 x float> %b0, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
274 %5 = shufflevector <2 x float> %b1, <2 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1>
275 %6 = select <4 x i1> <i1 false, i1 false, i1 true, i1 true>, <4 x float> %5, <4 x float> %4
276 %7 = fsub <4 x float> %3, %6
277 ret <4 x float> %7
278}