Blame - llvm/lib/Target/R600/SIInstrInfo.h - toolchain/llvm-project

blob: 72bb25e369f673cc14b754ca96eb7218467e2f0f [file] [log] [blame]

Matt Arsenault	df90c02	2013-10-15 23:44:45 +0000	[diff] [blame]	1	//===-- SIInstrInfo.h - SI Instruction Info Interface ------------ C++ --===//
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	2	//
				3	// The LLVM Compiler Infrastructure
				4	//
				5	// This file is distributed under the University of Illinois Open Source
				6	// License. See LICENSE.TXT for details.
				7	//
				8	//===----------------------------------------------------------------------===//
				9	//
				10	/// \file
				11	/// \brief Interface definition for SIInstrInfo.
				12	//
				13	//===----------------------------------------------------------------------===//
				14
				15
				16	#ifndef SIINSTRINFO_H
				17	#define SIINSTRINFO_H
				18
				19	#include "AMDGPUInstrInfo.h"
				20	#include "SIRegisterInfo.h"
				21
				22	namespace llvm {
				23
				24	class SIInstrInfo : public AMDGPUInstrInfo {
				25	private:
				26	const SIRegisterInfo RI;
				27
				28	public:
				29	explicit SIInstrInfo(AMDGPUTargetMachine &tm);
				30
				31	const SIRegisterInfo &getRegisterInfo() const;
				32
				33	virtual void copyPhysReg(MachineBasicBlock &MBB,
				34	MachineBasicBlock::iterator MI, DebugLoc DL,
				35	unsigned DestReg, unsigned SrcReg,
				36	bool KillSrc) const;
				37
Christian Konig	3c14580	2013-03-27 09:12:59 +0000	[diff] [blame]	38	unsigned commuteOpcode(unsigned Opcode) const;
				39
Christian Konig	76edd4f	2013-02-26 17:52:29 +0000	[diff] [blame]	40	virtual MachineInstr commuteInstruction(MachineInstr MI,
				41	bool NewMI=false) const;
				42
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	43	virtual unsigned getIEQOpcode() const { assert(!"Implement"); return 0;}
Tom Stellard	26a3b67	2013-10-22 18:19:10 +0000	[diff] [blame]	44	MachineInstr buildMovInstr(MachineBasicBlock MBB,
				45	MachineBasicBlock::iterator I,
				46	unsigned DstReg, unsigned SrcReg) const;
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	47	virtual bool isMov(unsigned Opcode) const;
				48
				49	virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
Tom Stellard	16a9a20	2013-08-14 23:24:17 +0000	[diff] [blame]	50	int isMIMG(uint16_t Opcode) const;
Michel Danzer	20680b1	2013-08-16 16:19:24 +0000	[diff] [blame]	51	int isSMRD(uint16_t Opcode) const;
Tom Stellard	93fabce	2013-10-10 17:11:55 +0000	[diff] [blame]	52	bool isVOP1(uint16_t Opcode) const;
				53	bool isVOP2(uint16_t Opcode) const;
				54	bool isVOP3(uint16_t Opcode) const;
				55	bool isVOPC(uint16_t Opcode) const;
				56	bool isInlineConstant(const MachineOperand &MO) const;
				57	bool isLiteralConstant(const MachineOperand &MO) const;
Tom Stellard	f3b2a1e	2013-02-06 17:32:29 +0000	[diff] [blame]	58
Tom Stellard	93fabce	2013-10-10 17:11:55 +0000	[diff] [blame]	59	virtual bool verifyInstruction(const MachineInstr *MI,
				60	StringRef &ErrInfo) const;
Tom Stellard	f3b2a1e	2013-02-06 17:32:29 +0000	[diff] [blame]	61	virtual int getIndirectIndexBegin(const MachineFunction &MF) const;
				62
				63	virtual int getIndirectIndexEnd(const MachineFunction &MF) const;
				64
				65	virtual unsigned calculateIndirectAddress(unsigned RegIndex,
				66	unsigned Channel) const;
				67
Tom Stellard	26a3b67	2013-10-22 18:19:10 +0000	[diff] [blame]	68	virtual const TargetRegisterClass *getIndirectAddrRegClass() const;
Tom Stellard	f3b2a1e	2013-02-06 17:32:29 +0000	[diff] [blame]	69
				70	virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
				71	MachineBasicBlock::iterator I,
				72	unsigned ValueReg,
				73	unsigned Address,
				74	unsigned OffsetReg) const;
				75
				76	virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
				77	MachineBasicBlock::iterator I,
				78	unsigned ValueReg,
				79	unsigned Address,
				80	unsigned OffsetReg) const;
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	81	};
				82
Christian Konig	f741fbf	2013-02-26 17:52:42 +0000	[diff] [blame]	83	namespace AMDGPU {
				84
				85	int getVOPe64(uint16_t Opcode);
Christian Konig	3c14580	2013-03-27 09:12:59 +0000	[diff] [blame]	86	int getCommuteRev(uint16_t Opcode);
				87	int getCommuteOrig(uint16_t Opcode);
Christian Konig	f741fbf	2013-02-26 17:52:42 +0000	[diff] [blame]	88
				89	} // End namespace AMDGPU
				90
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	91	} // End namespace llvm
				92
				93	namespace SIInstrFlags {
				94	enum Flags {
				95	// First 4 bits are the instruction encoding
Tom Stellard	1c822a8	2013-02-07 19:39:45 +0000	[diff] [blame]	96	VM_CNT = 1 << 0,
				97	EXP_CNT = 1 << 1,
				98	LGKM_CNT = 1 << 2
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	99	};
				100	}
				101
				102	#endif //SIINSTRINFO_H