Blame - llvm/lib/Target/R600/SIInstrInfo.h - toolchain/llvm-project

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Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	1	//===-- SIInstrInfo.h - SI Instruction Info Interface ---------------------===//
				2	//
				3	// The LLVM Compiler Infrastructure
				4	//
				5	// This file is distributed under the University of Illinois Open Source
				6	// License. See LICENSE.TXT for details.
				7	//
				8	//===----------------------------------------------------------------------===//
				9	//
				10	/// \file
				11	/// \brief Interface definition for SIInstrInfo.
				12	//
				13	//===----------------------------------------------------------------------===//
				14
				15
				16	#ifndef SIINSTRINFO_H
				17	#define SIINSTRINFO_H
				18
				19	#include "AMDGPUInstrInfo.h"
				20	#include "SIRegisterInfo.h"
				21
				22	namespace llvm {
				23
				24	class SIInstrInfo : public AMDGPUInstrInfo {
				25	private:
				26	const SIRegisterInfo RI;
				27
				28	public:
				29	explicit SIInstrInfo(AMDGPUTargetMachine &tm);
				30
				31	const SIRegisterInfo &getRegisterInfo() const;
				32
				33	virtual void copyPhysReg(MachineBasicBlock &MBB,
				34	MachineBasicBlock::iterator MI, DebugLoc DL,
				35	unsigned DestReg, unsigned SrcReg,
				36	bool KillSrc) const;
				37
Christian Konig	3c14580	2013-03-27 09:12:59 +0000	[diff] [blame]	38	unsigned commuteOpcode(unsigned Opcode) const;
				39
Christian Konig	76edd4f	2013-02-26 17:52:29 +0000	[diff] [blame]	40	virtual MachineInstr commuteInstruction(MachineInstr MI,
				41	bool NewMI=false) const;
				42
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	43	virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg,
				44	int64_t Imm) const;
				45
				46	virtual unsigned getIEQOpcode() const { assert(!"Implement"); return 0;}
				47	virtual bool isMov(unsigned Opcode) const;
				48
				49	virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
Tom Stellard	16a9a20	2013-08-14 23:24:17 +0000	[diff] [blame]	50	int isMIMG(uint16_t Opcode) const;
Michel Danzer	20680b1	2013-08-16 16:19:24 +0000	[diff] [blame]	51	int isSMRD(uint16_t Opcode) const;
Tom Stellard	93fabce	2013-10-10 17:11:55 +0000	[diff] [blame^]	52	bool isVOP1(uint16_t Opcode) const;
				53	bool isVOP2(uint16_t Opcode) const;
				54	bool isVOP3(uint16_t Opcode) const;
				55	bool isVOPC(uint16_t Opcode) const;
				56	bool isInlineConstant(const MachineOperand &MO) const;
				57	bool isLiteralConstant(const MachineOperand &MO) const;
Tom Stellard	f3b2a1e	2013-02-06 17:32:29 +0000	[diff] [blame]	58
Tom Stellard	93fabce	2013-10-10 17:11:55 +0000	[diff] [blame^]	59	virtual bool verifyInstruction(const MachineInstr *MI,
				60	StringRef &ErrInfo) const;
Tom Stellard	f3b2a1e	2013-02-06 17:32:29 +0000	[diff] [blame]	61	virtual int getIndirectIndexBegin(const MachineFunction &MF) const;
				62
				63	virtual int getIndirectIndexEnd(const MachineFunction &MF) const;
				64
				65	virtual unsigned calculateIndirectAddress(unsigned RegIndex,
				66	unsigned Channel) const;
				67
				68	virtual const TargetRegisterClass *getIndirectAddrStoreRegClass(
				69	unsigned SourceReg) const;
				70
				71	virtual const TargetRegisterClass *getIndirectAddrLoadRegClass() const;
				72
				73	virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
				74	MachineBasicBlock::iterator I,
				75	unsigned ValueReg,
				76	unsigned Address,
				77	unsigned OffsetReg) const;
				78
				79	virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
				80	MachineBasicBlock::iterator I,
				81	unsigned ValueReg,
				82	unsigned Address,
				83	unsigned OffsetReg) const;
				84
				85	virtual const TargetRegisterClass *getSuperIndirectRegClass() const;
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	86	};
				87
Christian Konig	f741fbf	2013-02-26 17:52:42 +0000	[diff] [blame]	88	namespace AMDGPU {
				89
				90	int getVOPe64(uint16_t Opcode);
Christian Konig	3c14580	2013-03-27 09:12:59 +0000	[diff] [blame]	91	int getCommuteRev(uint16_t Opcode);
				92	int getCommuteOrig(uint16_t Opcode);
Christian Konig	f741fbf	2013-02-26 17:52:42 +0000	[diff] [blame]	93
				94	} // End namespace AMDGPU
				95
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	96	} // End namespace llvm
				97
				98	namespace SIInstrFlags {
				99	enum Flags {
				100	// First 4 bits are the instruction encoding
Tom Stellard	1c822a8	2013-02-07 19:39:45 +0000	[diff] [blame]	101	VM_CNT = 1 << 0,
				102	EXP_CNT = 1 << 1,
				103	LGKM_CNT = 1 << 2
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	104	};
				105	}
				106
				107	#endif //SIINSTRINFO_H