| Nikolai Bozhenov | 82f0801 | 2017-05-29 09:48:30 +0000 | [diff] [blame^] | 1 | //===- Nios2InstrInfo.td - Target Description for Nios2 ------*- tablegen -*-=// | 
|  | 2 | // | 
|  | 3 | //                     The LLVM Compiler Infrastructure | 
|  | 4 | // | 
|  | 5 | // This file is distributed under the University of Illinois Open Source | 
|  | 6 | // License. See LICENSE.TXT for details. | 
|  | 7 | // | 
|  | 8 | //===----------------------------------------------------------------------===// | 
|  | 9 | // | 
|  | 10 | // This file contains the Nios2 implementation of the TargetInstrInfo class. | 
|  | 11 | // | 
|  | 12 | //===----------------------------------------------------------------------===// | 
|  | 13 |  | 
|  | 14 | //===----------------------------------------------------------------------===// | 
|  | 15 | // Instruction format superclass | 
|  | 16 | //===----------------------------------------------------------------------===// | 
|  | 17 |  | 
|  | 18 | include "Nios2InstrFormats.td" | 
|  | 19 |  | 
|  | 20 | //===----------------------------------------------------------------------===// | 
|  | 21 | // Nios2 Operand, Complex Patterns and Transformations Definitions. | 
|  | 22 | //===----------------------------------------------------------------------===// | 
|  | 23 |  | 
|  | 24 | def simm16      : Operand<i32> { | 
|  | 25 | let DecoderMethod= "DecodeSimm16"; | 
|  | 26 | } | 
|  | 27 |  | 
|  | 28 | // Node immediate fits as 16-bit sign extended on target immediate. | 
|  | 29 | // e.g. addi, andi | 
|  | 30 | def immSExt16  : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>; | 
|  | 31 |  | 
|  | 32 | //===----------------------------------------------------------------------===// | 
|  | 33 | // Instructions specific format | 
|  | 34 | //===----------------------------------------------------------------------===// | 
|  | 35 |  | 
|  | 36 | // Arithmetic and logical instructions with 2 register operands. | 
|  | 37 | class ArithLogicI<bits<6> op, string instr_asm, SDNode OpNode, | 
|  | 38 | Operand Od, PatLeaf imm_type, RegisterClass RC> : | 
|  | 39 | FI<op, (outs RC:$rB), (ins RC:$rA, Od:$imm16), | 
|  | 40 | !strconcat(instr_asm, "\t$rB, $rA, $imm16"), | 
|  | 41 | [(set RC:$rB, (OpNode RC:$rA, imm_type:$imm16))]> { | 
|  | 42 | let isReMaterializable = 1; | 
|  | 43 | } | 
|  | 44 |  | 
|  | 45 | //===----------------------------------------------------------------------===// | 
|  | 46 | // Nios2 R1 Instructions | 
|  | 47 | //===----------------------------------------------------------------------===// | 
|  | 48 |  | 
|  | 49 | /// Arithmetic Instructions (ALU Immediate) | 
|  | 50 | def ADDi : ArithLogicI<0x04, "addi", add, simm16, immSExt16, CPURegs>; |