| Andrew Trick | 85a1d4c | 2013-04-24 15:54:43 +0000 | [diff] [blame^] | 1 | ; REQUIRES: asserts |
| 2 | ; RUN: llc < %s -march=thumb -mcpu=swift -pre-RA-sched=source -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s |
| 3 | ; |
| 4 | ; Loop counter copies should be eliminated. |
| 5 | ; There is also a MUL here, but we don't care where it is scheduled. |
| 6 | ; CHECK: postinc |
| 7 | ; CHECK: *** Final schedule for BB#2 *** |
| 8 | ; CHECK: t2LDRs |
| 9 | ; CHECK: t2ADDrr |
| 10 | ; CHECK: t2CMPrr |
| 11 | ; CHECK: COPY |
| 12 | define i32 @postinc(i32 %a, i32* nocapture %d, i32 %s) nounwind { |
| 13 | entry: |
| 14 | %cmp4 = icmp eq i32 %a, 0 |
| 15 | br i1 %cmp4, label %for.end, label %for.body |
| 16 | |
| 17 | for.body: ; preds = %entry, %for.body |
| 18 | %indvars.iv = phi i32 [ %indvars.iv.next, %for.body ], [ 0, %entry ] |
| 19 | %s.05 = phi i32 [ %mul, %for.body ], [ 0, %entry ] |
| 20 | %indvars.iv.next = add i32 %indvars.iv, %s |
| 21 | %arrayidx = getelementptr inbounds i32* %d, i32 %indvars.iv |
| 22 | %0 = load i32* %arrayidx, align 4 |
| 23 | %mul = mul nsw i32 %0, %s.05 |
| 24 | %exitcond = icmp eq i32 %indvars.iv.next, %a |
| 25 | br i1 %exitcond, label %for.end, label %for.body |
| 26 | |
| 27 | for.end: ; preds = %for.body, %entry |
| 28 | %s.0.lcssa = phi i32 [ 0, %entry ], [ %mul, %for.body ] |
| 29 | ret i32 %s.0.lcssa |
| 30 | } |