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gerrit-public.fairphone.software / toolchain / llvm-project / 864c9537735811aec6de34032d7fefa48fdf141f / . / llvm / test / CodeGen / PowerPC / testComparesineull.ll
blob: 7f0fed15157c55d6938260aef6adf25c83745c76 [file] [log] [blame]
Nemanja Ivanovic864c9532017-07-25 17:54:51 +0000[diff] [blame^]1; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
3; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
4; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
6; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
7; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
8
9@glob = common local_unnamed_addr global i64 0, align 8
10
11define signext i32 @test_ineull(i64 %a, i64 %b) {
12; CHECK-LABEL: test_ineull:
13; CHECK: # BB#0: # %entry
14; CHECK-NEXT: xor r3, r3, r4
15; CHECK-NEXT: addic r4, r3, -1
16; CHECK-NEXT: subfe r3, r4, r3
17; CHECK-NEXT: blr
18entry:
19 %cmp = icmp ne i64 %a, %b
20 %conv = zext i1 %cmp to i32
21 ret i32 %conv
22}
23
24define signext i32 @test_ineull_sext(i64 %a, i64 %b) {
25; CHECK-LABEL: test_ineull_sext:
26; CHECK: # BB#0: # %entry
27; CHECK-NEXT: xor r3, r3, r4
28; CHECK-NEXT: subfic r3, r3, 0
29; CHECK-NEXT: subfe r3, r3, r3
30; CHECK-NEXT: blr
31entry:
32 %cmp = icmp ne i64 %a, %b
33 %sub = sext i1 %cmp to i32
34 ret i32 %sub
35}
36
37define signext i32 @test_ineull_z(i64 %a) {
38; CHECK-LABEL: test_ineull_z:
39; CHECK: # BB#0: # %entry
40; CHECK-NEXT: addic r4, r3, -1
41; CHECK-NEXT: subfe r3, r4, r3
42; CHECK-NEXT: blr
43entry:
44 %cmp = icmp ne i64 %a, 0
45 %conv = zext i1 %cmp to i32
46 ret i32 %conv
47}
48
49define signext i32 @test_ineull_sext_z(i64 %a) {
50; CHECK-LABEL: test_ineull_sext_z:
51; CHECK: # BB#0: # %entry
52; CHECK-NEXT: subfic r3, r3, 0
53; CHECK-NEXT: subfe r3, r3, r3
54; CHECK-NEXT: blr
55entry:
56 %cmp = icmp ne i64 %a, 0
57 %sub = sext i1 %cmp to i32
58 ret i32 %sub
59}
60
61define void @test_ineull_store(i64 %a, i64 %b) {
62; CHECK-LABEL: test_ineull_store:
63; CHECK: # BB#0: # %entry
64; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
65; CHECK-NEXT: xor r3, r3, r4
66; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
67; CHECK-NEXT: addic r5, r3, -1
68; CHECK-NEXT: subfe r3, r5, r3
69; CHECK-NEXT: std r3, 0(r12)
70; CHECK-NEXT: blr
71entry:
72 %cmp = icmp ne i64 %a, %b
73 %conv1 = zext i1 %cmp to i64
74 store i64 %conv1, i64* @glob, align 8
75 ret void
76}
77
78define void @test_ineull_sext_store(i64 %a, i64 %b) {
79; CHECK-LABEL: test_ineull_sext_store:
80; CHECK: # BB#0: # %entry
81; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
82; CHECK-NEXT: xor r3, r3, r4
83; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
84; CHECK-NEXT: subfic r3, r3, 0
85; CHECK-NEXT: subfe r3, r3, r3
86; CHECK-NEXT: std r3, 0(r12)
87; CHECK-NEXT: blr
88entry:
89 %cmp = icmp ne i64 %a, %b
90 %conv1 = sext i1 %cmp to i64
91 store i64 %conv1, i64* @glob, align 8
92 ret void
93}
94
95define void @test_ineull_z_store(i64 %a) {
96; CHECK-LABEL: test_ineull_z_store:
97; CHECK: # BB#0: # %entry
98; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
99; CHECK-NEXT: addic r5, r3, -1
100; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
101; CHECK-NEXT: subfe r3, r5, r3
102; CHECK-NEXT: std r3, 0(r4)
103; CHECK-NEXT: blr
104entry:
105 %cmp = icmp ne i64 %a, 0
106 %conv1 = zext i1 %cmp to i64
107 store i64 %conv1, i64* @glob, align 8
108 ret void
109}
110
111define void @test_ineull_sext_z_store(i64 %a) {
112; CHECK-LABEL: test_ineull_sext_z_store:
113; CHECK: # BB#0: # %entry
114; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
115; CHECK-NEXT: subfic r3, r3, 0
116; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
117; CHECK-NEXT: subfe r3, r3, r3
118; CHECK-NEXT: std r3, 0(r4)
119; CHECK-NEXT: blr
120entry:
121 %cmp = icmp ne i64 %a, 0
122 %conv1 = sext i1 %cmp to i64
123 store i64 %conv1, i64* @glob, align 8
124 ret void
125}