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gerrit-public.fairphone.software / toolchain / llvm-project / 87982a1e9b42b18e803a2dda3a79ff665b7b2243 / . / llvm / test / CodeGen / PowerPC / fast-isel-conversion.ll
blob: b0e29c1274a24225a1391dc4748a5b517f309b11 [file] [log] [blame]
Bill Schmidt87982a12014-10-19 20:48:47 +0000[diff] [blame^]1; FIXME: FastISel currently returns false if it hits code that uses VSX
2; registers and with -fast-isel-abort turned on the test case will then fail.
3; When fastisel better supports VSX fix up this test case.
4;
5; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s --check-prefix=ELF64
6; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx | FileCheck %s --check-prefix=ELF64LE
7; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=970 -mattr=-vsx | FileCheck %s --check-prefix=PPC970
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]8
9;; Tests for 970 don't use -fast-isel-abort because we intentionally punt
10;; to SelectionDAG in some cases.
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]11
12; Test sitofp
13
14define void @sitofp_single_i64(i64 %a, float %b) nounwind ssp {
15entry:
16; ELF64: sitofp_single_i64
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]17; ELF64LE: sitofp_single_i64
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]18; PPC970: sitofp_single_i64
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]19 %b.addr = alloca float, align 4
20 %conv = sitofp i64 %a to float
21; ELF64: std
22; ELF64: lfd
23; ELF64: fcfids
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]24; ELF64LE: std
25; ELF64LE: lfd
26; ELF64LE: fcfids
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]27; PPC970: std
28; PPC970: lfd
29; PPC970: fcfid
30; PPC970: frsp
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]31 store float %conv, float* %b.addr, align 4
32 ret void
33}
34
35define void @sitofp_single_i32(i32 %a, float %b) nounwind ssp {
36entry:
37; ELF64: sitofp_single_i32
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]38; ELF64LE: sitofp_single_i32
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]39; PPC970: sitofp_single_i32
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]40 %b.addr = alloca float, align 4
41 %conv = sitofp i32 %a to float
42; ELF64: std
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]43; stack offset used to load the float: 65524 = -16 + 4
44; ELF64: ori {{[0-9]+}}, {{[0-9]+}}, 65524
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]45; ELF64: lfiwax
46; ELF64: fcfids
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]47; ELF64LE: std
48; stack offset used to load the float: 65520 = -16 + 0
49; ELF64LE: ori {{[0-9]+}}, {{[0-9]+}}, 65520
50; ELF64LE: lfiwax
51; ELF64LE: fcfids
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]52; PPC970: std
53; PPC970: lfd
54; PPC970: fcfid
55; PPC970: frsp
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]56 store float %conv, float* %b.addr, align 4
57 ret void
58}
59
60define void @sitofp_single_i16(i16 %a, float %b) nounwind ssp {
61entry:
62; ELF64: sitofp_single_i16
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]63; ELF64LE: sitofp_single_i16
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]64; PPC970: sitofp_single_i16
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]65 %b.addr = alloca float, align 4
66 %conv = sitofp i16 %a to float
67; ELF64: extsh
68; ELF64: std
69; ELF64: lfd
70; ELF64: fcfids
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]71; ELF64LE: extsh
72; ELF64LE: std
73; ELF64LE: lfd
74; ELF64LE: fcfids
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]75; PPC970: extsh
76; PPC970: std
77; PPC970: lfd
78; PPC970: fcfid
79; PPC970: frsp
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]80 store float %conv, float* %b.addr, align 4
81 ret void
82}
83
84define void @sitofp_single_i8(i8 %a) nounwind ssp {
85entry:
86; ELF64: sitofp_single_i8
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]87; ELF64LE: sitofp_single_i8
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]88; PPC970: sitofp_single_i8
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]89 %b.addr = alloca float, align 4
90 %conv = sitofp i8 %a to float
91; ELF64: extsb
92; ELF64: std
93; ELF64: lfd
94; ELF64: fcfids
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]95; ELF64LE: extsb
96; ELF64LE: std
97; ELF64LE: lfd
98; ELF64LE: fcfids
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]99; PPC970: extsb
100; PPC970: std
101; PPC970: lfd
102; PPC970: fcfid
103; PPC970: frsp
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]104 store float %conv, float* %b.addr, align 4
105 ret void
106}
107
108define void @sitofp_double_i32(i32 %a, double %b) nounwind ssp {
109entry:
110; ELF64: sitofp_double_i32
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]111; ELF64LE: sitofp_double_i32
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]112; PPC970: sitofp_double_i32
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]113 %b.addr = alloca double, align 8
114 %conv = sitofp i32 %a to double
115; ELF64: std
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]116; stack offset used to load the float: 65524 = -16 + 4
117; ELF64: ori {{[0-9]+}}, {{[0-9]+}}, 65524
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]118; ELF64: lfiwax
119; ELF64: fcfid
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]120; ELF64LE: std
121; stack offset used to load the float: 65520 = -16 + 0
122; ELF64LE: ori {{[0-9]+}}, {{[0-9]+}}, 65520
123; ELF64LE: lfiwax
124; ELF64LE: fcfid
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]125; PPC970: std
126; PPC970: lfd
127; PPC970: fcfid
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]128 store double %conv, double* %b.addr, align 8
129 ret void
130}
131
132define void @sitofp_double_i64(i64 %a, double %b) nounwind ssp {
133entry:
134; ELF64: sitofp_double_i64
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]135; ELF64LE: sitofp_double_i64
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]136; PPC970: sitofp_double_i64
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]137 %b.addr = alloca double, align 8
138 %conv = sitofp i64 %a to double
139; ELF64: std
140; ELF64: lfd
141; ELF64: fcfid
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]142; ELF64LE: std
143; ELF64LE: lfd
144; ELF64LE: fcfid
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]145; PPC970: std
146; PPC970: lfd
147; PPC970: fcfid
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]148 store double %conv, double* %b.addr, align 8
149 ret void
150}
151
152define void @sitofp_double_i16(i16 %a, double %b) nounwind ssp {
153entry:
154; ELF64: sitofp_double_i16
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]155; ELF64LE: sitofp_double_i16
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]156; PPC970: sitofp_double_i16
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]157 %b.addr = alloca double, align 8
158 %conv = sitofp i16 %a to double
159; ELF64: extsh
160; ELF64: std
161; ELF64: lfd
162; ELF64: fcfid
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]163; ELF64LE: extsh
164; ELF64LE: std
165; ELF64LE: lfd
166; ELF64LE: fcfid
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]167; PPC970: extsh
168; PPC970: std
169; PPC970: lfd
170; PPC970: fcfid
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]171 store double %conv, double* %b.addr, align 8
172 ret void
173}
174
175define void @sitofp_double_i8(i8 %a, double %b) nounwind ssp {
176entry:
177; ELF64: sitofp_double_i8
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]178; ELF64LE: sitofp_double_i8
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]179; PPC970: sitofp_double_i8
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]180 %b.addr = alloca double, align 8
181 %conv = sitofp i8 %a to double
182; ELF64: extsb
183; ELF64: std
184; ELF64: lfd
185; ELF64: fcfid
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]186; ELF64LE: extsb
187; ELF64LE: std
188; ELF64LE: lfd
189; ELF64LE: fcfid
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]190; PPC970: extsb
191; PPC970: std
192; PPC970: lfd
193; PPC970: fcfid
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]194 store double %conv, double* %b.addr, align 8
195 ret void
196}
197
198; Test uitofp
199
200define void @uitofp_single_i64(i64 %a, float %b) nounwind ssp {
201entry:
202; ELF64: uitofp_single_i64
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]203; ELF64LE: uitofp_single_i64
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]204; PPC970: uitofp_single_i64
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]205 %b.addr = alloca float, align 4
206 %conv = uitofp i64 %a to float
207; ELF64: std
208; ELF64: lfd
209; ELF64: fcfidus
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]210; ELF64LE: std
211; ELF64LE: lfd
212; ELF64LE: fcfidus
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]213; PPC970-NOT: fcfidus
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]214 store float %conv, float* %b.addr, align 4
215 ret void
216}
217
218define void @uitofp_single_i32(i32 %a, float %b) nounwind ssp {
219entry:
220; ELF64: uitofp_single_i32
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]221; ELF64LE: uitofp_single_i32
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]222; PPC970: uitofp_single_i32
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]223 %b.addr = alloca float, align 4
224 %conv = uitofp i32 %a to float
225; ELF64: std
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]226; stack offset used to load the float: 65524 = -16 + 4
227; ELF64: ori {{[0-9]+}}, {{[0-9]+}}, 65524
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]228; ELF64: lfiwzx
229; ELF64: fcfidus
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]230; ELF64LE: std
231; stack offset used to load the float: 65520 = -16 + 0
232; ELF64LE: ori {{[0-9]+}}, {{[0-9]+}}, 65520
233; ELF64LE: lfiwzx
234; ELF64LE: fcfidus
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]235; PPC970-NOT: lfiwzx
236; PPC970-NOT: fcfidus
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]237 store float %conv, float* %b.addr, align 4
238 ret void
239}
240
241define void @uitofp_single_i16(i16 %a, float %b) nounwind ssp {
242entry:
243; ELF64: uitofp_single_i16
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]244; ELF64LE: uitofp_single_i16
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]245; PPC970: uitofp_single_i16
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]246 %b.addr = alloca float, align 4
247 %conv = uitofp i16 %a to float
248; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48
249; ELF64: std
250; ELF64: lfd
251; ELF64: fcfidus
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]252; ELF64LE: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48
253; ELF64LE: std
254; ELF64LE: lfd
255; ELF64LE: fcfidus
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]256; PPC970: rlwinm {{[0-9]+}}, {{[0-9]+}}, 0, 16, 31
257; PPC970: std
258; PPC970: lfd
259; PPC970: fcfid
260; PPC970: frsp
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]261 store float %conv, float* %b.addr, align 4
262 ret void
263}
264
265define void @uitofp_single_i8(i8 %a) nounwind ssp {
266entry:
267; ELF64: uitofp_single_i8
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]268; ELF64LE: uitofp_single_i8
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]269; PPC970: uitofp_single_i8
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]270 %b.addr = alloca float, align 4
271 %conv = uitofp i8 %a to float
272; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56
273; ELF64: std
274; ELF64: lfd
275; ELF64: fcfidus
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]276; ELF64LE: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56
277; ELF64LE: std
278; ELF64LE: lfd
279; ELF64LE: fcfidus
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]280; PPC970: rlwinm {{[0-9]+}}, {{[0-9]+}}, 0, 24, 31
281; PPC970: std
282; PPC970: lfd
283; PPC970: fcfid
284; PPC970: frsp
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]285 store float %conv, float* %b.addr, align 4
286 ret void
287}
288
289define void @uitofp_double_i64(i64 %a, double %b) nounwind ssp {
290entry:
291; ELF64: uitofp_double_i64
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]292; ELF64LE: uitofp_double_i64
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]293; PPC970: uitofp_double_i64
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]294 %b.addr = alloca double, align 8
295 %conv = uitofp i64 %a to double
296; ELF64: std
297; ELF64: lfd
298; ELF64: fcfidu
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]299; ELF64LE: std
300; ELF64LE: lfd
301; ELF64LE: fcfidu
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]302; PPC970-NOT: fcfidu
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]303 store double %conv, double* %b.addr, align 8
304 ret void
305}
306
307define void @uitofp_double_i32(i32 %a, double %b) nounwind ssp {
308entry:
309; ELF64: uitofp_double_i32
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]310; ELF64LE: uitofp_double_i32
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]311; PPC970: uitofp_double_i32
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]312 %b.addr = alloca double, align 8
313 %conv = uitofp i32 %a to double
314; ELF64: std
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]315; stack offset used to load the float: 65524 = -16 + 4
316; ELF64: ori {{[0-9]+}}, {{[0-9]+}}, 65524
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]317; ELF64: lfiwzx
318; ELF64: fcfidu
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]319; ELF64LE: std
320; stack offset used to load the float: 65520 = -16 + 0
321; ELF64LE: ori {{[0-9]+}}, {{[0-9]+}}, 65520
322; ELF64LE: lfiwzx
323; ELF64LE: fcfidu
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]324; PPC970-NOT: lfiwzx
325; PPC970-NOT: fcfidu
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]326 store double %conv, double* %b.addr, align 8
327 ret void
328}
329
330define void @uitofp_double_i16(i16 %a, double %b) nounwind ssp {
331entry:
332; ELF64: uitofp_double_i16
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]333; ELF64LE: uitofp_double_i16
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]334; PPC970: uitofp_double_i16
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]335 %b.addr = alloca double, align 8
336 %conv = uitofp i16 %a to double
337; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48
338; ELF64: std
339; ELF64: lfd
340; ELF64: fcfidu
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]341; ELF64LE: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48
342; ELF64LE: std
343; ELF64LE: lfd
344; ELF64LE: fcfidu
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]345; PPC970: rlwinm {{[0-9]+}}, {{[0-9]+}}, 0, 16, 31
346; PPC970: std
347; PPC970: lfd
348; PPC970: fcfid
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]349 store double %conv, double* %b.addr, align 8
350 ret void
351}
352
353define void @uitofp_double_i8(i8 %a, double %b) nounwind ssp {
354entry:
355; ELF64: uitofp_double_i8
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]356; ELF64LE: uitofp_double_i8
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]357; PPC970: uitofp_double_i8
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]358 %b.addr = alloca double, align 8
359 %conv = uitofp i8 %a to double
360; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56
361; ELF64: std
362; ELF64: lfd
363; ELF64: fcfidu
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]364; ELF64LE: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56
365; ELF64LE: std
366; ELF64LE: lfd
367; ELF64LE: fcfidu
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]368; PPC970: rlwinm {{[0-9]+}}, {{[0-9]+}}, 0, 24, 31
369; PPC970: std
370; PPC970: lfd
371; PPC970: fcfid
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]372 store double %conv, double* %b.addr, align 8
373 ret void
374}
375
376; Test fptosi
377
378define void @fptosi_float_i32(float %a) nounwind ssp {
379entry:
380; ELF64: fptosi_float_i32
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]381; ELF64LE: fptosi_float_i32
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]382; PPC970: fptosi_float_i32
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]383 %b.addr = alloca i32, align 4
384 %conv = fptosi float %a to i32
385; ELF64: fctiwz
386; ELF64: stfd
387; ELF64: lwa
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]388; ELF64LE: fctiwz
389; ELF64LE: stfd
390; ELF64LE: lwa
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]391; PPC970: fctiwz
392; PPC970: stfd
393; PPC970: lwa
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]394 store i32 %conv, i32* %b.addr, align 4
395 ret void
396}
397
398define void @fptosi_float_i64(float %a) nounwind ssp {
399entry:
400; ELF64: fptosi_float_i64
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]401; ELF64LE: fptosi_float_i64
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]402; PPC970: fptosi_float_i64
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]403 %b.addr = alloca i64, align 4
404 %conv = fptosi float %a to i64
405; ELF64: fctidz
406; ELF64: stfd
407; ELF64: ld
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]408; ELF64LE: fctidz
409; ELF64LE: stfd
410; ELF64LE: ld
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]411; PPC970: fctidz
412; PPC970: stfd
413; PPC970: ld
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]414 store i64 %conv, i64* %b.addr, align 4
415 ret void
416}
417
418define void @fptosi_double_i32(double %a) nounwind ssp {
419entry:
420; ELF64: fptosi_double_i32
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]421; ELF64LE: fptosi_double_i32
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]422; PPC970: fptosi_double_i32
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]423 %b.addr = alloca i32, align 8
424 %conv = fptosi double %a to i32
425; ELF64: fctiwz
426; ELF64: stfd
427; ELF64: lwa
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]428; ELF64LE: fctiwz
429; ELF64LE: stfd
430; ELF64LE: lwa
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]431; PPC970: fctiwz
432; PPC970: stfd
433; PPC970: lwa
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]434 store i32 %conv, i32* %b.addr, align 8
435 ret void
436}
437
438define void @fptosi_double_i64(double %a) nounwind ssp {
439entry:
440; ELF64: fptosi_double_i64
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]441; ELF64LE: fptosi_double_i64
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]442; PPC970: fptosi_double_i64
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]443 %b.addr = alloca i64, align 8
444 %conv = fptosi double %a to i64
445; ELF64: fctidz
446; ELF64: stfd
447; ELF64: ld
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]448; ELF64LE: fctidz
449; ELF64LE: stfd
450; ELF64LE: ld
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]451; PPC970: fctidz
452; PPC970: stfd
453; PPC970: ld
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]454 store i64 %conv, i64* %b.addr, align 8
455 ret void
456}
457
458; Test fptoui
459
460define void @fptoui_float_i32(float %a) nounwind ssp {
461entry:
462; ELF64: fptoui_float_i32
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]463; ELF64LE: fptoui_float_i32
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]464; PPC970: fptoui_float_i32
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]465 %b.addr = alloca i32, align 4
466 %conv = fptoui float %a to i32
467; ELF64: fctiwuz
468; ELF64: stfd
469; ELF64: lwz
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]470; ELF64LE: fctiwuz
471; ELF64LE: stfd
472; ELF64LE: lwz
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]473; PPC970: fctidz
474; PPC970: stfd
475; PPC970: lwz
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]476 store i32 %conv, i32* %b.addr, align 4
477 ret void
478}
479
480define void @fptoui_float_i64(float %a) nounwind ssp {
481entry:
482; ELF64: fptoui_float_i64
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]483; ELF64LE: fptoui_float_i64
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]484; PPC970: fptoui_float_i64
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]485 %b.addr = alloca i64, align 4
486 %conv = fptoui float %a to i64
487; ELF64: fctiduz
488; ELF64: stfd
489; ELF64: ld
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]490; ELF64LE: fctiduz
491; ELF64LE: stfd
492; ELF64LE: ld
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]493; PPC970-NOT: fctiduz
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]494 store i64 %conv, i64* %b.addr, align 4
495 ret void
496}
497
498define void @fptoui_double_i32(double %a) nounwind ssp {
499entry:
500; ELF64: fptoui_double_i32
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]501; ELF64LE: fptoui_double_i32
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]502; PPC970: fptoui_double_i32
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]503 %b.addr = alloca i32, align 8
504 %conv = fptoui double %a to i32
505; ELF64: fctiwuz
506; ELF64: stfd
507; ELF64: lwz
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]508; ELF64LE: fctiwuz
509; ELF64LE: stfd
510; ELF64LE: lwz
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]511; PPC970: fctidz
512; PPC970: stfd
513; PPC970: lwz
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]514 store i32 %conv, i32* %b.addr, align 8
515 ret void
516}
517
518define void @fptoui_double_i64(double %a) nounwind ssp {
519entry:
520; ELF64: fptoui_double_i64
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]521; ELF64LE: fptoui_double_i64
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]522; PPC970: fptoui_double_i64
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]523 %b.addr = alloca i64, align 8
524 %conv = fptoui double %a to i64
525; ELF64: fctiduz
526; ELF64: stfd
527; ELF64: ld
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]528; ELF64LE: fctiduz
529; ELF64LE: stfd
530; ELF64LE: ld
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]531; PPC970-NOT: fctiduz
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]532 store i64 %conv, i64* %b.addr, align 8
533 ret void
534}