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gerrit-public.fairphone.software / toolchain / llvm-project / 8abaf8954a97f20d0fd036e8e32e4b69d23f342e / . / llvm / lib / Target / Hexagon / HexagonPatternsHVX.td
blob: 0e5436411cf5bf853e551975427d7d7cc6f51bbb [file] [log] [blame]
Krzysztof Parzyszek8abaf892018-02-06 20:22:20 +0000[diff] [blame^]1def SDTVecLeaf:
2 SDTypeProfile<1, 0, [SDTCisVec<0>]>;
3def SDTVecBinOp:
4 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<1,2>]>;
5
6def SDTHexagonVEXTRACTW: SDTypeProfile<1, 2,
7 [SDTCisVT<0, i32>, SDTCisVec<1>, SDTCisVT<2, i32>]>;
8def HexagonVEXTRACTW : SDNode<"HexagonISD::VEXTRACTW", SDTHexagonVEXTRACTW>;
9
10def SDTHexagonVINSERTW0: SDTypeProfile<1, 2,
11 [SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisVT<2, i32>]>;
12def HexagonVINSERTW0 : SDNode<"HexagonISD::VINSERTW0", SDTHexagonVINSERTW0>;
13
14def HwLen2: SDNodeXForm<imm, [{
15 const auto &ST = static_cast<const HexagonSubtarget&>(CurDAG->getSubtarget());
16 return CurDAG->getTargetConstant(ST.getVectorLength()/2, SDLoc(N), MVT::i32);
17}]>;
18
19def Q2V: OutPatFrag<(ops node:$Qs), (V6_vandqrt $Qs, (A2_tfrsi -1))>;
20
21def Combinev: OutPatFrag<(ops node:$Vs, node:$Vt),
22 (REG_SEQUENCE HvxWR, $Vs, vsub_hi, $Vt, vsub_lo)>;
23
24def Combineq: OutPatFrag<(ops node:$Qs, node:$Qt),
25 (V6_vandvrt
26 (V6_vor
27 (V6_vror (V6_vpackeb (V6_vd0), (Q2V $Qs)),
28 (A2_tfrsi (HwLen2 (i32 0)))), // Half the vector length
29 (V6_vpackeb (V6_vd0), (Q2V $Qt))),
30 (A2_tfrsi -1))>;
31
32def LoVec: OutPatFrag<(ops node:$Vs), (EXTRACT_SUBREG $Vs, vsub_lo)>;
33def HiVec: OutPatFrag<(ops node:$Vs), (EXTRACT_SUBREG $Vs, vsub_hi)>;
34
35def HexagonVZERO: SDNode<"HexagonISD::VZERO", SDTVecLeaf>;
36def HexagonQCAT: SDNode<"HexagonISD::QCAT", SDTVecBinOp>;
37def HexagonQTRUE: SDNode<"HexagonISD::QTRUE", SDTVecLeaf>;
38def HexagonQFALSE: SDNode<"HexagonISD::QFALSE", SDTVecLeaf>;
39def vzero: PatFrag<(ops), (HexagonVZERO)>;
40def qtrue: PatFrag<(ops), (HexagonQTRUE)>;
41def qfalse: PatFrag<(ops), (HexagonQFALSE)>;
42def qcat: PatFrag<(ops node:$Qs, node:$Qt),
43 (HexagonQCAT node:$Qs, node:$Qt)>;
44
45def qnot: PatFrag<(ops node:$Qs), (xor node:$Qs, qtrue)>;
46
47def VSxtb: OutPatFrag<(ops node:$Vs), (V6_vunpackb $Vs)>;
48def VSxth: OutPatFrag<(ops node:$Vs), (V6_vunpackh $Vs)>;
49def VZxtb: OutPatFrag<(ops node:$Vs), (V6_vunpackub $Vs)>;
50def VZxth: OutPatFrag<(ops node:$Vs), (V6_vunpackuh $Vs)>;
51
52def SplatB: SDNodeXForm<imm, [{
53 uint32_t V = N->getZExtValue();
54 assert(isUInt<8>(V));
55 uint32_t S = V << 24 | V << 16 | V << 8 | V;
56 return CurDAG->getTargetConstant(S, SDLoc(N), MVT::i32);
57}]>;
58
59def SplatH: SDNodeXForm<imm, [{
60 uint32_t V = N->getZExtValue();
61 assert(isUInt<16>(V));
62 return CurDAG->getTargetConstant(V << 16 | V, SDLoc(N), MVT::i32);
63}]>;
64
65
66// HVX loads
67
68multiclass HvxLd_pat<InstHexagon MI, PatFrag Load, ValueType VT,
69 PatFrag ImmPred> {
70 def: Pat<(VT (Load I32:$Rt)), (MI I32:$Rt, 0)>;
71 def: Pat<(VT (Load (add I32:$Rt, ImmPred:$s))), (MI I32:$Rt, imm:$s)>;
72 // The HVX selection code for shuffles can generate vector constants.
73 // Calling "Select" on the resulting loads from CP fails without these
74 // patterns.
75 def: Pat<(VT (Load (HexagonCP tconstpool:$A))), (MI (A2_tfrsi imm:$A), 0)>;
76 def: Pat<(VT (Load (HexagonAtPcrel tconstpool:$A))),
77 (MI (C4_addipc imm:$A), 0)>;
78}
79
80let Predicates = [UseHVX] in {
81 multiclass HvxLdVs_pat<InstHexagon MI, PatFrag Load> {
82 defm: HvxLd_pat<MI, Load, VecI8, IsVecOff>;
83 defm: HvxLd_pat<MI, Load, VecI16, IsVecOff>;
84 defm: HvxLd_pat<MI, Load, VecI32, IsVecOff>;
85 }
86 defm: HvxLdVs_pat<V6_vL32b_nt_ai, alignednontemporalload>;
87 defm: HvxLdVs_pat<V6_vL32b_ai, alignedload>;
88 defm: HvxLdVs_pat<V6_vL32Ub_ai, unalignedload>;
89
90 multiclass HvxLdWs_pat<InstHexagon MI, PatFrag Load> {
91 defm: HvxLd_pat<MI, Load, VecPI8, IsVecOff>;
92 defm: HvxLd_pat<MI, Load, VecPI16, IsVecOff>;
93 defm: HvxLd_pat<MI, Load, VecPI32, IsVecOff>;
94 }
95 defm: HvxLdWs_pat<PS_vloadrw_nt_ai, alignednontemporalload>;
96 defm: HvxLdWs_pat<PS_vloadrw_ai, alignedload>;
97 defm: HvxLdWs_pat<PS_vloadrwu_ai, unalignedload>;
98}
99
100
101// HVX stores
102
103multiclass HvxSt_pat<InstHexagon MI, PatFrag Store, PatFrag ImmPred,
104 PatFrag Value> {
105 def: Pat<(Store Value:$Vs, I32:$Rt),
106 (MI I32:$Rt, 0, Value:$Vs)>;
107 def: Pat<(Store Value:$Vs, (add I32:$Rt, ImmPred:$s)),
108 (MI I32:$Rt, imm:$s, Value:$Vs)>;
109}
110
111let Predicates = [UseHVX] in {
112 multiclass HvxStVs_pat<InstHexagon MI, PatFrag Store> {
113 defm: HvxSt_pat<MI, Store, IsVecOff, HVI8>;
114 defm: HvxSt_pat<MI, Store, IsVecOff, HVI16>;
115 defm: HvxSt_pat<MI, Store, IsVecOff, HVI32>;
116 }
117 defm: HvxStVs_pat<V6_vS32b_nt_ai, alignednontemporalstore>;
118 defm: HvxStVs_pat<V6_vS32b_ai, alignedstore>;
119 defm: HvxStVs_pat<V6_vS32Ub_ai, unalignedstore>;
120
121 multiclass HvxStWs_pat<InstHexagon MI, PatFrag Store> {
122 defm: HvxSt_pat<MI, Store, IsVecOff, HWI8>;
123 defm: HvxSt_pat<MI, Store, IsVecOff, HWI16>;
124 defm: HvxSt_pat<MI, Store, IsVecOff, HWI32>;
125 }
126 defm: HvxStWs_pat<PS_vstorerw_nt_ai, alignednontemporalstore>;
127 defm: HvxStWs_pat<PS_vstorerw_ai, alignedstore>;
128 defm: HvxStWs_pat<PS_vstorerwu_ai, unalignedstore>;
129}
130
131
132let Predicates = [UseHVX] in {
133 def: Pat<(VecI8 vzero), (V6_vd0)>;
134 def: Pat<(VecI16 vzero), (V6_vd0)>;
135 def: Pat<(VecI32 vzero), (V6_vd0)>;
136 // Use V6_vsubw_dv instead.
137 def: Pat<(VecPI8 vzero), (Combinev (V6_vd0), (V6_vd0))>;
138 def: Pat<(VecPI16 vzero), (Combinev (V6_vd0), (V6_vd0))>;
139 def: Pat<(VecPI32 vzero), (Combinev (V6_vd0), (V6_vd0))>;
140
141 def: Pat<(VecPI8 (concat_vectors HVI8:$Vs, HVI8:$Vt)),
142 (Combinev HvxVR:$Vt, HvxVR:$Vs)>;
143 def: Pat<(VecPI16 (concat_vectors HVI16:$Vs, HVI16:$Vt)),
144 (Combinev HvxVR:$Vt, HvxVR:$Vs)>;
145 def: Pat<(VecPI32 (concat_vectors HVI32:$Vs, HVI32:$Vt)),
146 (Combinev HvxVR:$Vt, HvxVR:$Vs)>;
147
148 def: Pat<(VecQ8 (qcat HQ16:$Qs, HQ16:$Qt)), (Combineq $Qs, $Qt)>;
149 def: Pat<(VecQ16 (qcat HQ32:$Qs, HQ32:$Qt)), (Combineq $Qs, $Qt)>;
150
151 def: Pat<(HexagonVEXTRACTW HVI8:$Vu, I32:$Rs),
152 (V6_extractw HvxVR:$Vu, I32:$Rs)>;
153 def: Pat<(HexagonVEXTRACTW HVI16:$Vu, I32:$Rs),
154 (V6_extractw HvxVR:$Vu, I32:$Rs)>;
155 def: Pat<(HexagonVEXTRACTW HVI32:$Vu, I32:$Rs),
156 (V6_extractw HvxVR:$Vu, I32:$Rs)>;
157
158 def: Pat<(HexagonVINSERTW0 HVI8:$Vu, I32:$Rt),
159 (V6_vinsertwr HvxVR:$Vu, I32:$Rt)>;
160 def: Pat<(HexagonVINSERTW0 HVI16:$Vu, I32:$Rt),
161 (V6_vinsertwr HvxVR:$Vu, I32:$Rt)>;
162 def: Pat<(HexagonVINSERTW0 HVI32:$Vu, I32:$Rt),
163 (V6_vinsertwr HvxVR:$Vu, I32:$Rt)>;
164
165 let AddedComplexity = 10 in {
166 def: Pat<(VecI8 (HexagonVSPLAT u8_0ImmPred:$V)),
167 (V6_lvsplatw (ToI32 (SplatB $V)))>;
168 def: Pat<(VecI16 (HexagonVSPLAT u16_0ImmPred:$V)),
169 (V6_lvsplatw (ToI32 (SplatH $V)))>;
170 def: Pat<(VecI32 (HexagonVSPLAT anyimm:$V)),
171 (V6_lvsplatw (ToI32 $V))>;
172 def: Pat<(VecPI8 (HexagonVSPLAT u8_0ImmPred:$V)),
173 (Combinev (V6_lvsplatw (ToI32 (SplatB $V))),
174 (V6_lvsplatw (ToI32 (SplatB $V))))>;
175 def: Pat<(VecPI16 (HexagonVSPLAT u16_0ImmPred:$V)),
176 (Combinev (V6_lvsplatw (ToI32 (SplatH $V))),
177 (V6_lvsplatw (ToI32 (SplatH $V))))>;
178 def: Pat<(VecPI32 (HexagonVSPLAT anyimm:$V)),
179 (Combinev (V6_lvsplatw (ToI32 $V)), (V6_lvsplatw (ToI32 $V)))>;
180 }
181 def: Pat<(VecI8 (HexagonVSPLAT I32:$Rs)),
182 (V6_lvsplatw (S2_vsplatrb I32:$Rs))>;
183 def: Pat<(VecI16 (HexagonVSPLAT I32:$Rs)),
184 (V6_lvsplatw (A2_combine_ll I32:$Rs, I32:$Rs))>;
185 def: Pat<(VecI32 (HexagonVSPLAT I32:$Rs)),
186 (V6_lvsplatw I32:$Rs)>;
187 def: Pat<(VecPI8 (HexagonVSPLAT I32:$Rs)),
188 (Combinev (V6_lvsplatw (S2_vsplatrb I32:$Rs)),
189 (V6_lvsplatw (S2_vsplatrb I32:$Rs)))>;
190 def: Pat<(VecPI16 (HexagonVSPLAT I32:$Rs)),
191 (Combinev (V6_lvsplatw (A2_combine_ll I32:$Rs, I32:$Rs)),
192 (V6_lvsplatw (A2_combine_ll I32:$Rs, I32:$Rs)))>;
193 def: Pat<(VecPI32 (HexagonVSPLAT I32:$Rs)),
194 (Combinev (V6_lvsplatw I32:$Rs), (V6_lvsplatw I32:$Rs))>;
195
196 def: Pat<(add HVI8:$Vs, HVI8:$Vt), (V6_vaddb HvxVR:$Vs, HvxVR:$Vt)>;
197 def: Pat<(add HVI16:$Vs, HVI16:$Vt), (V6_vaddh HvxVR:$Vs, HvxVR:$Vt)>;
198 def: Pat<(add HVI32:$Vs, HVI32:$Vt), (V6_vaddw HvxVR:$Vs, HvxVR:$Vt)>;
199 def: Pat<(add HWI8:$Vs, HWI8:$Vt), (V6_vaddb_dv HvxWR:$Vs, HvxWR:$Vt)>;
200 def: Pat<(add HWI16:$Vs, HWI16:$Vt), (V6_vaddh_dv HvxWR:$Vs, HvxWR:$Vt)>;
201 def: Pat<(add HWI32:$Vs, HWI32:$Vt), (V6_vaddw_dv HvxWR:$Vs, HvxWR:$Vt)>;
202
203 def: Pat<(sub HVI8:$Vs, HVI8:$Vt), (V6_vsubb HvxVR:$Vs, HvxVR:$Vt)>;
204 def: Pat<(sub HVI16:$Vs, HVI16:$Vt), (V6_vsubh HvxVR:$Vs, HvxVR:$Vt)>;
205 def: Pat<(sub HVI32:$Vs, HVI32:$Vt), (V6_vsubw HvxVR:$Vs, HvxVR:$Vt)>;
206 def: Pat<(sub HWI8:$Vs, HWI8:$Vt), (V6_vsubb_dv HvxWR:$Vs, HvxWR:$Vt)>;
207 def: Pat<(sub HWI16:$Vs, HWI16:$Vt), (V6_vsubh_dv HvxWR:$Vs, HvxWR:$Vt)>;
208 def: Pat<(sub HWI32:$Vs, HWI32:$Vt), (V6_vsubw_dv HvxWR:$Vs, HvxWR:$Vt)>;
209
210 def: Pat<(and HVI8:$Vs, HVI8:$Vt), (V6_vand HvxVR:$Vs, HvxVR:$Vt)>;
211 def: Pat<(or HVI8:$Vs, HVI8:$Vt), (V6_vor HvxVR:$Vs, HvxVR:$Vt)>;
212 def: Pat<(xor HVI8:$Vs, HVI8:$Vt), (V6_vxor HvxVR:$Vs, HvxVR:$Vt)>;
213
214 def: Pat<(vselect HQ8:$Qu, HVI8:$Vs, HVI8:$Vt),
215 (V6_vmux HvxQR:$Qu, HvxVR:$Vs, HvxVR:$Vt)>;
216 def: Pat<(vselect HQ16:$Qu, HVI16:$Vs, HVI16:$Vt),
217 (V6_vmux HvxQR:$Qu, HvxVR:$Vs, HvxVR:$Vt)>;
218 def: Pat<(vselect HQ32:$Qu, HVI32:$Vs, HVI32:$Vt),
219 (V6_vmux HvxQR:$Qu, HvxVR:$Vs, HvxVR:$Vt)>;
220
221 def: Pat<(vselect (qnot HQ8:$Qu), HVI8:$Vs, HVI8:$Vt),
222 (V6_vmux HvxQR:$Qu, HvxVR:$Vt, HvxVR:$Vs)>;
223 def: Pat<(vselect (qnot HQ16:$Qu), HVI16:$Vs, HVI16:$Vt),
224 (V6_vmux HvxQR:$Qu, HvxVR:$Vt, HvxVR:$Vs)>;
225 def: Pat<(vselect (qnot HQ32:$Qu), HVI32:$Vs, HVI32:$Vt),
226 (V6_vmux HvxQR:$Qu, HvxVR:$Vt, HvxVR:$Vs)>;
227
228 def: Pat<(VecPI16 (sext HVI8:$Vs)), (VSxtb $Vs)>;
229 def: Pat<(VecPI32 (sext HVI16:$Vs)), (VSxth $Vs)>;
230 def: Pat<(VecPI16 (zext HVI8:$Vs)), (VZxtb $Vs)>;
231 def: Pat<(VecPI32 (zext HVI16:$Vs)), (VZxth $Vs)>;
232
233 def: Pat<(VecI16 (sext_invec HVI8:$Vs)), (LoVec (VSxtb $Vs))>;
234 def: Pat<(VecI32 (sext_invec HVI16:$Vs)), (LoVec (VSxth $Vs))>;
235 def: Pat<(VecI32 (sext_invec HVI8:$Vs)),
236 (LoVec (VSxth (LoVec (VSxtb $Vs))))>;
237 def: Pat<(VecPI16 (sext_invec HWI8:$Vss)), (VSxtb (LoVec $Vss))>;
238 def: Pat<(VecPI32 (sext_invec HWI16:$Vss)), (VSxth (LoVec $Vss))>;
239 def: Pat<(VecPI32 (sext_invec HWI8:$Vss)),
240 (VSxth (LoVec (VSxtb (LoVec $Vss))))>;
241
242 def: Pat<(VecI16 (zext_invec HVI8:$Vs)), (LoVec (VZxtb $Vs))>;
243 def: Pat<(VecI32 (zext_invec HVI16:$Vs)), (LoVec (VZxth $Vs))>;
244 def: Pat<(VecI32 (zext_invec HVI8:$Vs)),
245 (LoVec (VZxth (LoVec (VZxtb $Vs))))>;
246 def: Pat<(VecPI16 (zext_invec HWI8:$Vss)), (VZxtb (LoVec $Vss))>;
247 def: Pat<(VecPI32 (zext_invec HWI16:$Vss)), (VZxth (LoVec $Vss))>;
248 def: Pat<(VecPI32 (zext_invec HWI8:$Vss)),
249 (VZxth (LoVec (VZxtb (LoVec $Vss))))>;
250
251 // The "source" types are not legal, and there are no parameterized
252 // definitions for them, but they are length-specific.
253 let Predicates = [UseHVX,UseHVX64B] in {
254 def: Pat<(VecI16 (sext_inreg HVI16:$Vs, v32i8)),
255 (V6_vasrh (V6_vaslh HVI16:$Vs, (A2_tfrsi 8)), (A2_tfrsi 8))>;
256 def: Pat<(VecI32 (sext_inreg HVI32:$Vs, v16i8)),
257 (V6_vasrw (V6_vaslw HVI32:$Vs, (A2_tfrsi 24)), (A2_tfrsi 24))>;
258 def: Pat<(VecI32 (sext_inreg HVI32:$Vs, v16i16)),
259 (V6_vasrw (V6_vaslw HVI32:$Vs, (A2_tfrsi 16)), (A2_tfrsi 16))>;
260 }
261 let Predicates = [UseHVX,UseHVX128B] in {
262 def: Pat<(VecI16 (sext_inreg HVI16:$Vs, v64i8)),
263 (V6_vasrh (V6_vaslh HVI16:$Vs, (A2_tfrsi 8)), (A2_tfrsi 8))>;
264 def: Pat<(VecI32 (sext_inreg HVI32:$Vs, v32i8)),
265 (V6_vasrw (V6_vaslw HVI32:$Vs, (A2_tfrsi 24)), (A2_tfrsi 24))>;
266 def: Pat<(VecI32 (sext_inreg HVI32:$Vs, v32i16)),
267 (V6_vasrw (V6_vaslw HVI32:$Vs, (A2_tfrsi 16)), (A2_tfrsi 16))>;
268 }
269
270 def: Pat<(HexagonVASL HVI8:$Vs, I32:$Rt),
271 (V6_vpackeb (V6_vaslh (HiVec (VZxtb HvxVR:$Vs)), I32:$Rt),
272 (V6_vaslh (LoVec (VZxtb HvxVR:$Vs)), I32:$Rt))>;
273 def: Pat<(HexagonVASR HVI8:$Vs, I32:$Rt),
274 (V6_vpackeb (V6_vasrh (HiVec (VSxtb HvxVR:$Vs)), I32:$Rt),
275 (V6_vasrh (LoVec (VSxtb HvxVR:$Vs)), I32:$Rt))>;
276 def: Pat<(HexagonVLSR HVI8:$Vs, I32:$Rt),
277 (V6_vpackeb (V6_vlsrh (HiVec (VZxtb HvxVR:$Vs)), I32:$Rt),
278 (V6_vlsrh (LoVec (VZxtb HvxVR:$Vs)), I32:$Rt))>;
279
280 def: Pat<(HexagonVASL HVI16:$Vs, I32:$Rt), (V6_vaslh HvxVR:$Vs, I32:$Rt)>;
281 def: Pat<(HexagonVASL HVI32:$Vs, I32:$Rt), (V6_vaslw HvxVR:$Vs, I32:$Rt)>;
282 def: Pat<(HexagonVASR HVI16:$Vs, I32:$Rt), (V6_vasrh HvxVR:$Vs, I32:$Rt)>;
283 def: Pat<(HexagonVASR HVI32:$Vs, I32:$Rt), (V6_vasrw HvxVR:$Vs, I32:$Rt)>;
284 def: Pat<(HexagonVLSR HVI16:$Vs, I32:$Rt), (V6_vlsrh HvxVR:$Vs, I32:$Rt)>;
285 def: Pat<(HexagonVLSR HVI32:$Vs, I32:$Rt), (V6_vlsrw HvxVR:$Vs, I32:$Rt)>;
286
287 def: Pat<(shl HVI16:$Vs, HVI16:$Vt), (V6_vaslhv HvxVR:$Vs, HvxVR:$Vt)>;
288 def: Pat<(shl HVI32:$Vs, HVI32:$Vt), (V6_vaslwv HvxVR:$Vs, HvxVR:$Vt)>;
289 def: Pat<(sra HVI16:$Vs, HVI16:$Vt), (V6_vasrhv HvxVR:$Vs, HvxVR:$Vt)>;
290 def: Pat<(sra HVI32:$Vs, HVI32:$Vt), (V6_vasrwv HvxVR:$Vs, HvxVR:$Vt)>;
291 def: Pat<(srl HVI16:$Vs, HVI16:$Vt), (V6_vlsrhv HvxVR:$Vs, HvxVR:$Vt)>;
292 def: Pat<(srl HVI32:$Vs, HVI32:$Vt), (V6_vlsrwv HvxVR:$Vs, HvxVR:$Vt)>;
293
294 def: Pat<(vnot HQ8:$Qs), (V6_pred_not HvxQR:$Qs)>;
295 def: Pat<(vnot HQ16:$Qs), (V6_pred_not HvxQR:$Qs)>;
296 def: Pat<(vnot HQ32:$Qs), (V6_pred_not HvxQR:$Qs)>;
297 def: Pat<(qnot HQ8:$Qs), (V6_pred_not HvxQR:$Qs)>;
298 def: Pat<(qnot HQ16:$Qs), (V6_pred_not HvxQR:$Qs)>;
299 def: Pat<(qnot HQ32:$Qs), (V6_pred_not HvxQR:$Qs)>;
300
301 def: Pat<(VecQ8 (seteq HVI8:$Vs, HVI8:$Vt)),
302 (V6_veqb HvxVR:$Vs, HvxVR:$Vt)>;
303 def: Pat<(VecQ8 (setgt HVI8:$Vs, HVI8:$Vt)),
304 (V6_vgtb HvxVR:$Vs, HvxVR:$Vt)>;
305 def: Pat<(VecQ8 (setugt HVI8:$Vs, HVI8:$Vt)),
306 (V6_vgtub HvxVR:$Vs, HvxVR:$Vt)>;
307 def: Pat<(VecQ16 (seteq HVI16:$Vs, HVI16:$Vt)),
308 (V6_veqh HvxVR:$Vs, HvxVR:$Vt)>;
309 def: Pat<(VecQ16 (setgt HVI16:$Vs, HVI16:$Vt)),
310 (V6_vgth HvxVR:$Vs, HvxVR:$Vt)>;
311 def: Pat<(VecQ16 (setugt HVI16:$Vs, HVI16:$Vt)),
312 (V6_vgtuh HvxVR:$Vs, HvxVR:$Vt)>;
313 def: Pat<(VecQ32 (seteq HVI32:$Vs, HVI32:$Vt)),
314 (V6_veqw HvxVR:$Vs, HvxVR:$Vt)>;
315 def: Pat<(VecQ32 (setgt HVI32:$Vs, HVI32:$Vt)),
316 (V6_vgtw HvxVR:$Vs, HvxVR:$Vt)>;
317 def: Pat<(VecQ32 (setugt HVI32:$Vs, HVI32:$Vt)),
318 (V6_vgtuw HvxVR:$Vs, HvxVR:$Vt)>;
319
320 def: Pat<(VecI8 (trunc HWI16:$Vss)),
321 (V6_vpackeb (HiVec $Vss), (LoVec $Vss))>;
322 def: Pat<(VecI16 (trunc HWI32:$Vss)),
323 (V6_vpackeh (HiVec $Vss), (LoVec $Vss))>;
324}
325
326class HvxSel_pat<InstHexagon MI, PatFrag RegPred>
327 : Pat<(select I1:$Pu, RegPred:$Vs, RegPred:$Vt),
328 (MI I1:$Pu, RegPred:$Vs, RegPred:$Vt)>;
329
330let Predicates = [HasV60T,UseHVX] in {
331 def: HvxSel_pat<PS_vselect, HVI8>;
332 def: HvxSel_pat<PS_vselect, HVI16>;
333 def: HvxSel_pat<PS_vselect, HVI32>;
334 def: HvxSel_pat<PS_wselect, HWI8>;
335 def: HvxSel_pat<PS_wselect, HWI16>;
336 def: HvxSel_pat<PS_wselect, HWI32>;
337}
338