Blame - llvm/test/CodeGen/AMDGPU/llvm.pow.ll - toolchain/llvm-project

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Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	1	;RUN: llc < %s -march=r600 -mcpu=redwood \| FileCheck %s
				2
Tom Stellard	bfebd1f	2014-02-04 17:18:37 +0000	[diff] [blame]	3	;CHECK-LABEL: test1:
				4	;CHECK: LOG_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}},
				5	;CHECK-NEXT: MUL NON-IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}},
				6	;CHECK-NEXT: EXP_IEEE * T{{[0-9]+\.[XYZW], PV\.[XYZW]}},
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	7
Nicolai Haehnle	df3a20c	2016-04-06 19:40:20 +0000	[diff] [blame]	8	define amdgpu_ps void @test1(<4 x float> inreg %reg0) {
Vincent Lejeune	f143af3	2013-11-11 22:10:24 +0000	[diff] [blame]	9	%r0 = extractelement <4 x float> %reg0, i32 0
				10	%r1 = extractelement <4 x float> %reg0, i32 1
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	11	%r2 = call float @llvm.pow.f32( float %r0, float %r1)
Vincent Lejeune	f143af3	2013-11-11 22:10:24 +0000	[diff] [blame]	12	%vec = insertelement <4 x float> undef, float %r2, i32 0
Matt Arsenault	82e5e1e	2016-07-15 21:27:08 +0000	[diff] [blame]	13	call void @llvm.r600.store.swizzle(<4 x float> %vec, i32 0, i32 0)
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	14	ret void
				15	}
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Tom Stellard	bfebd1f	2014-02-04 17:18:37 +0000	[diff] [blame]	17	;CHECK-LABEL: test2:
				18	;CHECK: LOG_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}},
				19	;CHECK-NEXT: MUL NON-IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}},
				20	;CHECK-NEXT: LOG_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}},
				21	;CHECK-NEXT: MUL NON-IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}},
				22	;CHECK-NEXT: EXP_IEEE * T{{[0-9]+\.[XYZW], PV\.[XYZW]}},
				23	;CHECK-NEXT: EXP_IEEE * T{{[0-9]+\.[XYZW], PV\.[XYZW]}},
				24	;CHECK-NEXT: LOG_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}},
				25	;CHECK-NEXT: MUL NON-IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}},
				26	;CHECK-NEXT: LOG_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}},
				27	;CHECK-NEXT: MUL NON-IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}},
				28	;CHECK-NEXT: EXP_IEEE * T{{[0-9]+\.[XYZW], PV\.[XYZW]}},
				29	;CHECK-NEXT: EXP_IEEE * T{{[0-9]+\.[XYZW], PV\.[XYZW]}},
Nicolai Haehnle	df3a20c	2016-04-06 19:40:20 +0000	[diff] [blame]	30	define amdgpu_ps void @test2(<4 x float> inreg %reg0, <4 x float> inreg %reg1) {
Tom Stellard	bfebd1f	2014-02-04 17:18:37 +0000	[diff] [blame]	31	%vec = call <4 x float> @llvm.pow.v4f32( <4 x float> %reg0, <4 x float> %reg1)
Matt Arsenault	82e5e1e	2016-07-15 21:27:08 +0000	[diff] [blame]	32	call void @llvm.r600.store.swizzle(<4 x float> %vec, i32 0, i32 0)
Tom Stellard	bfebd1f	2014-02-04 17:18:37 +0000	[diff] [blame]	33	ret void
				34	}
				35
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	36	declare float @llvm.pow.f32(float ,float ) readonly
Tom Stellard	bfebd1f	2014-02-04 17:18:37 +0000	[diff] [blame]	37	declare <4 x float> @llvm.pow.v4f32(<4 x float> ,<4 x float> ) readonly
Matt Arsenault	82e5e1e	2016-07-15 21:27:08 +0000	[diff] [blame]	38	declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32)