blob: 2714b26c9141464d3b999b556523290b1f55befb [file] [log] [blame]
Andrea Di Biagioe85ba4d2014-05-08 17:44:04 +00001; RUN: llc < %s -march=x86-64 -mcpu=core-avx2 | FileCheck %s
2
3; Verify that the backend correctly combines AVX2 builtin intrinsics.
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5
Andrea Di Biagiod6211202014-05-15 15:18:15 +00006define <16 x i16> @test_x86_avx2_pblendw(<16 x i16> %a0) {
7 %res = call <16 x i16> @llvm.x86.avx2.pblendw(<16 x i16> %a0, <16 x i16> %a0, i32 7)
8 ret <16 x i16> %res
9}
10; CHECK-LABEL: test_x86_avx2_pblendw
11; CHECK-NOT: vpblendw
12; CHECK: ret
13
14
15define <4 x i32> @test_x86_avx2_pblendd_128(<4 x i32> %a0) {
16 %res = call <4 x i32> @llvm.x86.avx2.pblendd.128(<4 x i32> %a0, <4 x i32> %a0, i32 7)
17 ret <4 x i32> %res
18}
19; CHECK-LABEL: test_x86_avx2_pblendd_128
20; CHECK-NOT: vpblendd
21; CHECK: ret
22
23
24define <8 x i32> @test_x86_avx2_pblendd_256(<8 x i32> %a0) {
25 %res = call <8 x i32> @llvm.x86.avx2.pblendd.256(<8 x i32> %a0, <8 x i32> %a0, i32 7)
26 ret <8 x i32> %res
27}
28; CHECK-LABEL: test_x86_avx2_pblendd_256
29; CHECK-NOT: vpblendd
30; CHECK: ret
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32
Andrea Di Biagiod6211202014-05-15 15:18:15 +000033define <16 x i16> @test2_x86_avx2_pblendw(<16 x i16> %a0, <16 x i16> %a1) {
34 %res = call <16 x i16> @llvm.x86.avx2.pblendw(<16 x i16> %a0, <16 x i16> %a1, i32 0)
35 ret <16 x i16> %res
36}
37; CHECK-LABEL: test2_x86_avx2_pblendw
38; CHECK-NOT: vpblendw
39; CHECK: ret
40
41
42define <4 x i32> @test2_x86_avx2_pblendd_128(<4 x i32> %a0, <4 x i32> %a1) {
43 %res = call <4 x i32> @llvm.x86.avx2.pblendd.128(<4 x i32> %a0, <4 x i32> %a1, i32 0)
44 ret <4 x i32> %res
45}
46; CHECK-LABEL: test2_x86_avx2_pblendd_128
47; CHECK-NOT: vpblendd
48; CHECK: ret
49
50
51define <8 x i32> @test2_x86_avx2_pblendd_256(<8 x i32> %a0, <8 x i32> %a1) {
52 %res = call <8 x i32> @llvm.x86.avx2.pblendd.256(<8 x i32> %a0, <8 x i32> %a1, i32 0)
53 ret <8 x i32> %res
54}
55; CHECK-LABEL: test2_x86_avx2_pblendd_256
56; CHECK-NOT: vpblendd
57; CHECK: ret
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59
Andrea Di Biagiod6211202014-05-15 15:18:15 +000060define <16 x i16> @test3_x86_avx2_pblendw(<16 x i16> %a0, <16 x i16> %a1) {
61 %res = call <16 x i16> @llvm.x86.avx2.pblendw(<16 x i16> %a0, <16 x i16> %a1, i32 -1)
62 ret <16 x i16> %res
63}
64; CHECK-LABEL: test3_x86_avx2_pblendw
65; CHECK-NOT: vpblendw
66; CHECK: ret
67
68
69define <4 x i32> @test3_x86_avx2_pblendd_128(<4 x i32> %a0, <4 x i32> %a1) {
70 %res = call <4 x i32> @llvm.x86.avx2.pblendd.128(<4 x i32> %a0, <4 x i32> %a1, i32 -1)
71 ret <4 x i32> %res
72}
73; CHECK-LABEL: test3_x86_avx2_pblendd_128
74; CHECK-NOT: vpblendd
75; CHECK: ret
76
77
78define <8 x i32> @test3_x86_avx2_pblendd_256(<8 x i32> %a0, <8 x i32> %a1) {
79 %res = call <8 x i32> @llvm.x86.avx2.pblendd.256(<8 x i32> %a0, <8 x i32> %a1, i32 -1)
80 ret <8 x i32> %res
81}
82; CHECK-LABEL: test3_x86_avx2_pblendd_256
83; CHECK-NOT: vpblendd
84; CHECK: ret
85
86
Andrea Di Biagiod6211202014-05-15 15:18:15 +000087declare <16 x i16> @llvm.x86.avx2.pblendw(<16 x i16>, <16 x i16>, i32)
88declare <4 x i32> @llvm.x86.avx2.pblendd.128(<4 x i32>, <4 x i32>, i32)
89declare <8 x i32> @llvm.x86.avx2.pblendd.256(<8 x i32>, <8 x i32>, i32)
Andrea Di Biagioe85ba4d2014-05-08 17:44:04 +000090