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gerrit-public.fairphone.software / toolchain / llvm-project / 8d09a6c674dbd379c981ee9a58aa41eb3e648361 / . / llvm / lib / Target / Hexagon / HexagonInstrInfo.h
blob: 5da23cbfbf5f9b971eec83f3757a2f43f08c4e42 [file] [log] [blame]
Jia Liub22310f2012-02-18 12:03:15 +0000[diff] [blame]1//===- HexagonInstrInfo.h - Hexagon Instruction Information -----*- C++ -*-===//
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Hexagon implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef HexagonINSTRUCTIONINFO_H
15#define HexagonINSTRUCTIONINFO_H
16
Craig Topperb25fda92012-03-17 18:46:09 +0000[diff] [blame]17#include "HexagonRegisterInfo.h"
Brendon Cahoon6f358372012-02-08 18:25:47 +0000[diff] [blame]18#include "MCTargetDesc/HexagonBaseInfo.h"
Jyotsna Verma1d297502013-05-02 15:39:30 +0000[diff] [blame]19#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
Chandler Carruth8a8cd2b2014-01-07 11:48:04 +0000[diff] [blame]20#include "llvm/Target/TargetFrameLowering.h"
21#include "llvm/Target/TargetInstrInfo.h"
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]22
23#define GET_INSTRINFO_HEADER
24#include "HexagonGenInstrInfo.inc"
25
26namespace llvm {
27
Patrik Hagglund8d09a6c2014-03-15 09:11:41 +0000[diff] [blame^]28struct EVT;
29
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]30class HexagonInstrInfo : public HexagonGenInstrInfo {
Juergen Ributzkad12ccbd2013-11-19 00:57:56 +0000[diff] [blame]31 virtual void anchor();
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]32 const HexagonRegisterInfo RI;
Bill Wendling4a7a4082013-06-07 06:19:56 +0000[diff] [blame]33 const HexagonSubtarget &Subtarget;
Jyotsna Verma5ed51812013-05-01 21:37:34 +0000[diff] [blame]34 typedef unsigned Opcode_t;
35
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]36public:
37 explicit HexagonInstrInfo(HexagonSubtarget &ST);
38
39 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
40 /// such, whenever a client has an instance of instruction info, it should
41 /// always be able to get register info as well (through this method).
42 ///
43 virtual const HexagonRegisterInfo &getRegisterInfo() const { return RI; }
44
45 /// isLoadFromStackSlot - If the specified machine instruction is a direct
46 /// load from a stack slot, return the virtual or physical register number of
47 /// the destination along with the FrameIndex of the loaded stack slot. If
48 /// not, return 0. This predicate must return 0 if the instruction has
49 /// any side effects other than loading from the stack slot.
50 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
51 int &FrameIndex) const;
52
53 /// isStoreToStackSlot - If the specified machine instruction is a direct
54 /// store to a stack slot, return the virtual or physical register number of
55 /// the source reg along with the FrameIndex of the loaded stack slot. If
56 /// not, return 0. This predicate must return 0 if the instruction has
57 /// any side effects other than storing to the stack slot.
58 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
59 int &FrameIndex) const;
60
61
62 virtual bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
63 MachineBasicBlock *&FBB,
64 SmallVectorImpl<MachineOperand> &Cond,
65 bool AllowModify) const;
66
67 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
68
69 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
70 MachineBasicBlock *FBB,
71 const SmallVectorImpl<MachineOperand> &Cond,
72 DebugLoc DL) const;
73
Krzysztof Parzyszekcfe285e2013-02-11 20:04:29 +0000[diff] [blame]74 virtual bool analyzeCompare(const MachineInstr *MI,
75 unsigned &SrcReg, unsigned &SrcReg2,
76 int &Mask, int &Value) const;
77
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]78 virtual void copyPhysReg(MachineBasicBlock &MBB,
79 MachineBasicBlock::iterator I, DebugLoc DL,
80 unsigned DestReg, unsigned SrcReg,
81 bool KillSrc) const;
82
83 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
84 MachineBasicBlock::iterator MBBI,
85 unsigned SrcReg, bool isKill, int FrameIndex,
86 const TargetRegisterClass *RC,
87 const TargetRegisterInfo *TRI) const;
88
89 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
90 SmallVectorImpl<MachineOperand> &Addr,
91 const TargetRegisterClass *RC,
92 SmallVectorImpl<MachineInstr*> &NewMIs) const;
93
94 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
95 MachineBasicBlock::iterator MBBI,
96 unsigned DestReg, int FrameIndex,
97 const TargetRegisterClass *RC,
98 const TargetRegisterInfo *TRI) const;
99
100 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
101 SmallVectorImpl<MachineOperand> &Addr,
102 const TargetRegisterClass *RC,
103 SmallVectorImpl<MachineInstr*> &NewMIs) const;
104
105 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
106 MachineInstr* MI,
107 const SmallVectorImpl<unsigned> &Ops,
108 int FrameIndex) const;
109
110 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
111 MachineInstr* MI,
112 const SmallVectorImpl<unsigned> &Ops,
113 MachineInstr* LoadMI) const {
114 return 0;
115 }
116
117 unsigned createVR(MachineFunction* MF, MVT VT) const;
118
Jyotsna Verma84c47102013-05-06 18:49:23 +0000[diff] [blame]119 virtual bool isBranch(const MachineInstr *MI) const;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]120 virtual bool isPredicable(MachineInstr *MI) const;
121 virtual bool
122 PredicateInstruction(MachineInstr *MI,
123 const SmallVectorImpl<MachineOperand> &Cond) const;
124
Kay Tiong Khoof2949212012-06-13 15:53:04 +0000[diff] [blame]125 virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]126 unsigned ExtraPredCycles,
127 const BranchProbability &Probability) const;
128
129 virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
130 unsigned NumTCycles, unsigned ExtraTCycles,
131 MachineBasicBlock &FMBB,
132 unsigned NumFCycles, unsigned ExtraFCycles,
133 const BranchProbability &Probability) const;
134
135 virtual bool isPredicated(const MachineInstr *MI) const;
Jyotsna Verma84c47102013-05-06 18:49:23 +0000[diff] [blame]136 virtual bool isPredicated(unsigned Opcode) const;
137 virtual bool isPredicatedTrue(const MachineInstr *MI) const;
138 virtual bool isPredicatedTrue(unsigned Opcode) const;
Jyotsna Vermaa46059b2013-03-28 19:44:04 +0000[diff] [blame]139 virtual bool isPredicatedNew(const MachineInstr *MI) const;
Jyotsna Verma84c47102013-05-06 18:49:23 +0000[diff] [blame]140 virtual bool isPredicatedNew(unsigned Opcode) const;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]141 virtual bool DefinesPredicate(MachineInstr *MI,
142 std::vector<MachineOperand> &Pred) const;
143 virtual bool
144 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
145 const SmallVectorImpl<MachineOperand> &Pred2) const;
146
147 virtual bool
148 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
149
150 virtual bool
151 isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumCycles,
152 const BranchProbability &Probability) const;
153
Andrew Trickd06df962012-02-01 22:13:57 +0000[diff] [blame]154 virtual DFAPacketizer*
155 CreateTargetScheduleState(const TargetMachine *TM,
156 const ScheduleDAG *DAG) const;
157
158 virtual bool isSchedulingBoundary(const MachineInstr *MI,
159 const MachineBasicBlock *MBB,
160 const MachineFunction &MF) const;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]161 bool isValidOffset(const int Opcode, const int Offset) const;
162 bool isValidAutoIncImm(const EVT VT, const int Offset) const;
163 bool isMemOp(const MachineInstr *MI) const;
164 bool isSpillPredRegOp(const MachineInstr *MI) const;
165 bool isU6_3Immediate(const int value) const;
166 bool isU6_2Immediate(const int value) const;
167 bool isU6_1Immediate(const int value) const;
168 bool isU6_0Immediate(const int value) const;
169 bool isS4_3Immediate(const int value) const;
170 bool isS4_2Immediate(const int value) const;
171 bool isS4_1Immediate(const int value) const;
172 bool isS4_0Immediate(const int value) const;
173 bool isS12_Immediate(const int value) const;
174 bool isU6_Immediate(const int value) const;
175 bool isS8_Immediate(const int value) const;
176 bool isS6_Immediate(const int value) const;
177
Sirish Pandef8e5e3c2012-05-03 21:52:53 +0000[diff] [blame]178 bool isSaveCalleeSavedRegsCall(const MachineInstr* MI) const;
179 bool isConditionalTransfer(const MachineInstr* MI) const;
Chandler Carruth3c3bb552012-04-23 18:25:57 +0000[diff] [blame]180 bool isConditionalALU32 (const MachineInstr* MI) const;
181 bool isConditionalLoad (const MachineInstr* MI) const;
Sirish Pandef8e5e3c2012-05-03 21:52:53 +0000[diff] [blame]182 bool isConditionalStore(const MachineInstr* MI) const;
Jyotsna Vermaf1214a82013-03-05 18:51:42 +0000[diff] [blame]183 bool isNewValueInst(const MachineInstr* MI) const;
Jyotsna Verma84c47102013-05-06 18:49:23 +0000[diff] [blame]184 bool isNewValue(const MachineInstr* MI) const;
Jyotsna Vermaa46059b2013-03-28 19:44:04 +0000[diff] [blame]185 bool isDotNewInst(const MachineInstr* MI) const;
Jyotsna Verma438cec52013-05-10 20:58:11 +0000[diff] [blame]186 int GetDotOldOp(const int opc) const;
Jyotsna Verma300f0b92013-05-10 20:27:34 +0000[diff] [blame]187 int GetDotNewOp(const MachineInstr* MI) const;
Jyotsna Verma00681dc2013-05-09 19:16:07 +0000[diff] [blame]188 int GetDotNewPredOp(MachineInstr *MI,
189 const MachineBranchProbabilityInfo
190 *MBPI) const;
Jyotsna Verma438cec52013-05-10 20:58:11 +0000[diff] [blame]191 bool mayBeNewStore(const MachineInstr* MI) const;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]192 bool isDeallocRet(const MachineInstr *MI) const;
Chandler Carruth3c3bb552012-04-23 18:25:57 +0000[diff] [blame]193 unsigned getInvertedPredicatedOpcode(const int Opc) const;
Sirish Pandef8e5e3c2012-05-03 21:52:53 +0000[diff] [blame]194 bool isExtendable(const MachineInstr* MI) const;
195 bool isExtended(const MachineInstr* MI) const;
196 bool isPostIncrement(const MachineInstr* MI) const;
197 bool isNewValueStore(const MachineInstr* MI) const;
Jyotsna Verma300f0b92013-05-10 20:27:34 +0000[diff] [blame]198 bool isNewValueStore(unsigned Opcode) const;
Sirish Pandef8e5e3c2012-05-03 21:52:53 +0000[diff] [blame]199 bool isNewValueJump(const MachineInstr* MI) const;
Sirish Pande4bd20c52012-05-12 05:10:30 +0000[diff] [blame]200 bool isNewValueJumpCandidate(const MachineInstr *MI) const;
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]201
Jyotsna Verma84256432013-03-01 17:37:13 +0000[diff] [blame]202
203 void immediateExtend(MachineInstr *MI) const;
204 bool isConstExtended(MachineInstr *MI) const;
Jyotsna Verma1d297502013-05-02 15:39:30 +0000[diff] [blame]205 int getDotNewPredJumpOp(MachineInstr *MI,
206 const MachineBranchProbabilityInfo *MBPI) const;
Jyotsna Verma84256432013-03-01 17:37:13 +0000[diff] [blame]207 unsigned getAddrMode(const MachineInstr* MI) const;
208 bool isOperandExtended(const MachineInstr *MI,
209 unsigned short OperandNum) const;
210 unsigned short getCExtOpNum(const MachineInstr *MI) const;
211 int getMinValue(const MachineInstr *MI) const;
212 int getMaxValue(const MachineInstr *MI) const;
213 bool NonExtEquivalentExists (const MachineInstr *MI) const;
214 short getNonExtOpcode(const MachineInstr *MI) const;
Jyotsna Verma5ed51812013-05-01 21:37:34 +0000[diff] [blame]215 bool PredOpcodeHasJMP_c(Opcode_t Opcode) const;
216 bool PredOpcodeHasNot(Opcode_t Opcode) const;
217
Tony Linthicum1213a7a2011-12-12 21:14:40 +0000[diff] [blame]218private:
219 int getMatchingCondBranchOpcode(int Opc, bool sense) const;
220
221};
222
223}
224
225#endif