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gerrit-public.fairphone.software / toolchain / llvm-project / 8f14de8f32e63fffd37731dd2115d304ff3000a2 / . / llvm / lib / Target / X86 / X86InstrAVX512.td
blob: 884d7252c0658842ef394a7cffdcd2a2774bfedc [file] [log] [blame]
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1// Bitcasts between 512-bit vector types. Return the original type since
2// no instruction is needed for the conversion
3let Predicates = [HasAVX512] in {
4 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
5 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
6 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
7 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
8 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
9 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
10 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
11 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
12 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
13 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
14 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
15 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
16 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
17
18 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
19 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
20 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
21 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
22 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
23 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
24 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
25 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
26 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
27 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
28 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
29 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
30 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
31 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
32 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
33 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
34 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
35 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
36 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
37 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
38 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
39 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
40 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
41 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
42 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
43 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
44 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
45 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
46 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
47 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
48
49// Bitcasts between 256-bit vector types. Return the original type since
50// no instruction is needed for the conversion
51 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
52 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
53 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
54 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
55 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
56 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
57 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
58 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
59 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
60 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
61 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
62 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
63 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
64 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
65 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
66 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
67 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
68 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
69 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
70 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
71 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
72 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
73 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
74 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
75 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
76 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
77 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
78 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
79 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
80 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
81}
82
83//
84// AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
85//
86
87let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
88 isPseudo = 1, Predicates = [HasAVX512] in {
89def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
90 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
91}
92
93def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
94def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
95def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
96def : Pat<(v16f32 immAllZerosV), (AVX512_512_SET0)>;
97
98//===----------------------------------------------------------------------===//
99// AVX-512 - VECTOR INSERT
100//
101// -- 32x8 form --
102let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
103def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
104 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
105 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
106 []>, EVEX_4V, EVEX_V512;
107let mayLoad = 1 in
108def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
109 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
110 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
111 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
112}
113
114// -- 64x4 fp form --
115let neverHasSideEffects = 1, ExeDomain = SSEPackedDouble in {
116def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
117 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
118 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
119 []>, EVEX_4V, EVEX_V512, VEX_W;
120let mayLoad = 1 in
121def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
122 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
123 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
124 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
125}
126// -- 32x4 integer form --
127let neverHasSideEffects = 1 in {
128def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
129 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
130 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
131 []>, EVEX_4V, EVEX_V512;
132let mayLoad = 1 in
133def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
134 (ins VR512:$src1, i128mem:$src2, i8imm:$src3),
135 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
136 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
137
138}
139
140let neverHasSideEffects = 1 in {
141// -- 64x4 form --
142def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
143 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
144 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
145 []>, EVEX_4V, EVEX_V512, VEX_W;
146let mayLoad = 1 in
147def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
148 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
149 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
150 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
151}
152
153def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
154 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
155 (INSERT_get_vinsert128_imm VR512:$ins))>;
156def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
157 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
158 (INSERT_get_vinsert128_imm VR512:$ins))>;
159def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
160 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
161 (INSERT_get_vinsert128_imm VR512:$ins))>;
162def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
163 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
164 (INSERT_get_vinsert128_imm VR512:$ins))>;
165
166def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
167 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
168 (INSERT_get_vinsert128_imm VR512:$ins))>;
169def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
170 (bc_v4i32 (loadv2i64 addr:$src2)),
171 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
172 (INSERT_get_vinsert128_imm VR512:$ins))>;
173def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
174 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
175 (INSERT_get_vinsert128_imm VR512:$ins))>;
176def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
177 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
178 (INSERT_get_vinsert128_imm VR512:$ins))>;
179
180def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
181 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
182 (INSERT_get_vinsert256_imm VR512:$ins))>;
183def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
184 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
185 (INSERT_get_vinsert256_imm VR512:$ins))>;
186def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
187 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
188 (INSERT_get_vinsert256_imm VR512:$ins))>;
189def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
190 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
191 (INSERT_get_vinsert256_imm VR512:$ins))>;
192
193def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
194 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
195 (INSERT_get_vinsert256_imm VR512:$ins))>;
196def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
197 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
198 (INSERT_get_vinsert256_imm VR512:$ins))>;
199def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
200 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
201 (INSERT_get_vinsert256_imm VR512:$ins))>;
202def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
203 (bc_v8i32 (loadv4i64 addr:$src2)),
204 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
205 (INSERT_get_vinsert256_imm VR512:$ins))>;
206
207// vinsertps - insert f32 to XMM
208def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
209 (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
210 "vinsertps{z}\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
211 [(set VR128X:$dst, (X86insrtps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
212 EVEX_4V;
213def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
214 (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
215 "vinsertps{z}\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
216 [(set VR128X:$dst, (X86insrtps VR128X:$src1,
217 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
218 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
219
220//===----------------------------------------------------------------------===//
221// AVX-512 VECTOR EXTRACT
222//---
223let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
224// -- 32x4 form --
225def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
226 (ins VR512:$src1, i8imm:$src2),
227 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
228 []>, EVEX, EVEX_V512;
229def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
230 (ins f128mem:$dst, VR512:$src1, i8imm:$src2),
231 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
232 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
233
234// -- 64x4 form --
235def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
236 (ins VR512:$src1, i8imm:$src2),
237 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
238 []>, EVEX, EVEX_V512, VEX_W;
239let mayStore = 1 in
240def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
241 (ins f256mem:$dst, VR512:$src1, i8imm:$src2),
242 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
243 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
244}
245
246let neverHasSideEffects = 1 in {
247// -- 32x4 form --
248def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
249 (ins VR512:$src1, i8imm:$src2),
250 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
251 []>, EVEX, EVEX_V512;
252def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
253 (ins i128mem:$dst, VR512:$src1, i8imm:$src2),
254 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
255 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
256
257// -- 64x4 form --
258def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
259 (ins VR512:$src1, i8imm:$src2),
260 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
261 []>, EVEX, EVEX_V512, VEX_W;
262let mayStore = 1 in
263def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
264 (ins i256mem:$dst, VR512:$src1, i8imm:$src2),
265 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
266 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
267}
268
269def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
270 (v4f32 (VEXTRACTF32x4rr VR512:$src1,
271 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
272
273def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
274 (v4i32 (VEXTRACTF32x4rr VR512:$src1,
275 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
276
277def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
278 (v2f64 (VEXTRACTF32x4rr VR512:$src1,
279 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
280
281def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
282 (v2i64 (VEXTRACTI32x4rr VR512:$src1,
283 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
284
285
286def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
287 (v8f32 (VEXTRACTF64x4rr VR512:$src1,
288 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
289
290def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
291 (v8i32 (VEXTRACTI64x4rr VR512:$src1,
292 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
293
294def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
295 (v4f64 (VEXTRACTF64x4rr VR512:$src1,
296 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
297
298def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
299 (v4i64 (VEXTRACTI64x4rr VR512:$src1,
300 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
301
302// A 256-bit subvector extract from the first 512-bit vector position
303// is a subregister copy that needs no instruction.
304def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
305 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
306def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
307 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
308def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
309 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
310def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
311 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
312
313// zmm -> xmm
314def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
315 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
316def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
317 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
318def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
319 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
320def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
321 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
322
323
324// A 128-bit subvector insert to the first 512-bit vector position
325// is a subregister copy that needs no instruction.
326def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
327 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
328 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
329 sub_ymm)>;
330def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
331 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
332 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
333 sub_ymm)>;
334def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
335 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
336 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
337 sub_ymm)>;
338def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
339 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
340 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
341 sub_ymm)>;
342
343def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
344 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
345def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
346 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
347def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
348 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
349def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
350 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
351
352// vextractps - extract 32 bits from XMM
353def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
354 (ins VR128X:$src1, u32u8imm:$src2),
355 "vextractps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
356 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
357 EVEX;
358
359def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
360 (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2),
361 "vextractps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
362 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
363 addr:$dst)]>, EVEX;
364
365//===---------------------------------------------------------------------===//
366// AVX-512 BROADCAST
367//---
368multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
369 RegisterClass DestRC,
370 RegisterClass SrcRC, X86MemOperand x86memop> {
371 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
372 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
373 []>, EVEX;
374 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
375 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),[]>, EVEX;
376}
377let ExeDomain = SSEPackedSingle in {
378 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss{z}", VR512,
379 VR128X, f32mem>,
380 EVEX_V512, EVEX_CD8<32, CD8VT1>;
381}
382
383let ExeDomain = SSEPackedDouble in {
384 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd{z}", VR512,
385 VR128X, f64mem>,
386 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
387}
388
389def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
390 (VBROADCASTSSZrm addr:$src)>;
391def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
392 (VBROADCASTSDZrm addr:$src)>;
393
394multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
395 RegisterClass SrcRC, RegisterClass KRC> {
396 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
397 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
398 []>, EVEX, EVEX_V512;
399 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
400 (ins KRC:$mask, SrcRC:$src),
401 !strconcat(OpcodeStr,
402 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
403 []>, EVEX, EVEX_V512, EVEX_KZ;
404}
405
406defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
407defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
408 VEX_W;
409
410def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
411 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
412
413def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
414 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
415
416def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
417 (VPBROADCASTDrZrr GR32:$src)>;
418def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
419 (VPBROADCASTQrZrr GR64:$src)>;
420
421multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
422 X86MemOperand x86memop, PatFrag ld_frag,
423 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
424 RegisterClass KRC> {
425 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
426 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
427 [(set DstRC:$dst,
428 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
429 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
430 VR128X:$src),
431 !strconcat(OpcodeStr,
432 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
433 [(set DstRC:$dst,
434 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
435 EVEX, EVEX_KZ;
436 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
437 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
438 [(set DstRC:$dst,
439 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
440 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
441 x86memop:$src),
442 !strconcat(OpcodeStr,
443 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
444 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
445 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
446}
447
448defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
449 loadi32, VR512, v16i32, v4i32, VK16WM>,
450 EVEX_V512, EVEX_CD8<32, CD8VT1>;
451defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
452 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
453 EVEX_CD8<64, CD8VT1>;
454
455def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
456 (VBROADCASTSSZrr VR128X:$src)>;
457def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
458 (VBROADCASTSDZrr VR128X:$src)>;
459
460// Provide fallback in case the load node that is used in the patterns above
461// is used by additional users, which prevents the pattern selection.
462def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
463 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
464def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
465 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
466
467
468let Predicates = [HasAVX512] in {
469def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
470 (EXTRACT_SUBREG
471 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
472 addr:$src)), sub_ymm)>;
473}
474//===----------------------------------------------------------------------===//
475// AVX-512 BROADCAST MASK TO VECTOR REGISTER
476//---
477
478multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
479 RegisterClass DstRC, RegisterClass KRC,
480 ValueType OpVT, ValueType SrcVT> {
481def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
482 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
483 []>, EVEX;
484}
485
486defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
487 VK16, v16i32, v16i1>, EVEX_V512;
488defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
489 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
490
491//===----------------------------------------------------------------------===//
492// AVX-512 - VPERM
493//
494// -- immediate form --
495multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
496 SDNode OpNode, PatFrag mem_frag,
497 X86MemOperand x86memop, ValueType OpVT> {
498 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
499 (ins RC:$src1, i8imm:$src2),
500 !strconcat(OpcodeStr,
501 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
502 [(set RC:$dst,
503 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
504 EVEX;
505 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
506 (ins x86memop:$src1, i8imm:$src2),
507 !strconcat(OpcodeStr,
508 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
509 [(set RC:$dst,
510 (OpVT (OpNode (mem_frag addr:$src1),
511 (i8 imm:$src2))))]>, EVEX;
512}
513
514defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
515 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
516let ExeDomain = SSEPackedDouble in
517defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
518 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
519
520// -- VPERM - register form --
521multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
522 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
523
524 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
525 (ins RC:$src1, RC:$src2),
526 !strconcat(OpcodeStr,
527 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
528 [(set RC:$dst,
529 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
530
531 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
532 (ins RC:$src1, x86memop:$src2),
533 !strconcat(OpcodeStr,
534 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
535 [(set RC:$dst,
536 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
537 EVEX_4V;
538}
539
540defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
541 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
542defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
543 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
544let ExeDomain = SSEPackedSingle in
545defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
546 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
547let ExeDomain = SSEPackedDouble in
548defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
549 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
550
551// -- VPERM2I - 3 source operands form --
552multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
553 PatFrag mem_frag, X86MemOperand x86memop,
554 ValueType OpVT> {
555let Constraints = "$src1 = $dst" in {
556 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
557 (ins RC:$src1, RC:$src2, RC:$src3),
558 !strconcat(OpcodeStr,
559 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
560 [(set RC:$dst,
561 (OpVT (X86VPermv3 RC:$src1, RC:$src2, RC:$src3)))]>,
562 EVEX_4V;
563
564 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
565 (ins RC:$src1, RC:$src2, x86memop:$src3),
566 !strconcat(OpcodeStr,
567 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
568 [(set RC:$dst,
569 (OpVT (X86VPermv3 RC:$src1, RC:$src2,
570 (mem_frag addr:$src3))))]>, EVEX_4V;
571 }
572}
573defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32, i512mem,
574 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
575defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64, i512mem,
576 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
577defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32, i512mem,
578 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
579defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64, i512mem,
580 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
581
582//===----------------------------------------------------------------------===//
583// AVX-512 - BLEND using mask
584//
585multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
586 RegisterClass KRC, RegisterClass RC,
587 X86MemOperand x86memop, PatFrag mem_frag,
588 SDNode OpNode, ValueType vt> {
589 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
590 (ins KRC:$mask, RC:$src1, RC:$src2),
591 !strconcat(OpcodeStr,
592 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
593 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
594 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
595
596 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
597 (ins KRC:$mask, RC:$src1, x86memop:$src2),
598 !strconcat(OpcodeStr,
599 "\t{$src2, $src1, $mask, $dst|$dst, $mask, $src1, $src2}"),
600 []>,
601 EVEX_4V, EVEX_K;
602}
603
604let ExeDomain = SSEPackedSingle in
605defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps", VK16WM, VR512, f512mem,
606 memopv16f32, vselect, v16f32>,
607 EVEX_CD8<32, CD8VF>, EVEX_V512;
608let ExeDomain = SSEPackedDouble in
609defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd", VK8WM, VR512, f512mem,
610 memopv8f64, vselect, v8f64>,
611 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
612
613defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd", VK16WM, VR512, f512mem,
614 memopv8i64, vselect, v16i32>,
615 EVEX_CD8<32, CD8VF>, EVEX_V512;
616
617defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq", VK8WM, VR512, f512mem,
618 memopv8i64, vselect, v8i64>, VEX_W,
619 EVEX_CD8<64, CD8VF>, EVEX_V512;
620
621
622let Predicates = [HasAVX512] in {
623def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
624 (v8f32 VR256X:$src2))),
625 (EXTRACT_SUBREG
626 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
627 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
628 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
629
630def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
631 (v8i32 VR256X:$src2))),
632 (EXTRACT_SUBREG
633 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
634 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
635 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
636}
637
638multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC,
639 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
640 SDNode OpNode, ValueType vt> {
641 def rr : AVX512BI<opc, MRMSrcReg,
642 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
643 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
644 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
645 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
646 def rm : AVX512BI<opc, MRMSrcMem,
647 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
648 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
649 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2)))],
650 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
651}
652
653defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
654 memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512;
655defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
656 memopv8i64, X86pcmpeqm, v8i64>, T8, EVEX_V512, VEX_W;
657
658defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
659 memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512;
660defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
661 memopv8i64, X86pcmpgtm, v8i64>, T8, EVEX_V512, VEX_W;
662
663def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
664 (COPY_TO_REGCLASS (VPCMPGTDZrr
665 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
666 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
667
668def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
669 (COPY_TO_REGCLASS (VPCMPEQDZrr
670 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
671 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
672
673multiclass avx512_icmp_cc<bits<8> opc, RegisterClass KRC,
674 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
675 SDNode OpNode, ValueType vt, Operand CC, string asm,
676 string asm_alt> {
677 def rri : AVX512AIi8<opc, MRMSrcReg,
678 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
679 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))],
680 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
681 def rmi : AVX512AIi8<opc, MRMSrcMem,
682 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
683 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2),
684 imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
685 // Accept explicit immediate argument form instead of comparison code.
686 let neverHasSideEffects = 1 in {
687 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
688 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
689 asm_alt, [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
690 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
691 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
692 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
693 }
694}
695
696defm VPCMPDZ : avx512_icmp_cc<0x1F, VK16, VR512, i512mem, memopv16i32,
697 X86cmpm, v16i32, AVXCC,
698 "vpcmp${cc}d\t{$src2, $src1, $dst|$dst, $src1, $src2}",
699 "vpcmpd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
700 EVEX_V512, EVEX_CD8<32, CD8VF>;
701defm VPCMPUDZ : avx512_icmp_cc<0x1E, VK16, VR512, i512mem, memopv16i32,
702 X86cmpmu, v16i32, AVXCC,
703 "vpcmp${cc}ud\t{$src2, $src1, $dst|$dst, $src1, $src2}",
704 "vpcmpud\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
705 EVEX_V512, EVEX_CD8<32, CD8VF>;
706
707defm VPCMPQZ : avx512_icmp_cc<0x1F, VK8, VR512, i512mem, memopv8i64,
708 X86cmpm, v8i64, AVXCC,
709 "vpcmp${cc}q\t{$src2, $src1, $dst|$dst, $src1, $src2}",
710 "vpcmpq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
711 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
712defm VPCMPUQZ : avx512_icmp_cc<0x1E, VK8, VR512, i512mem, memopv8i64,
713 X86cmpmu, v8i64, AVXCC,
714 "vpcmp${cc}uq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
715 "vpcmpuq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
716 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
717
718// avx512_cmp_packed - sse 1 & 2 compare packed instructions
719multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
720 X86MemOperand x86memop, Operand CC,
721 SDNode OpNode, ValueType vt, string asm,
722 string asm_alt, Domain d> {
723 def rri : AVX512PIi8<0xC2, MRMSrcReg,
724 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
725 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
726 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
727 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
728 [(set KRC:$dst,
729 (OpNode (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
730
731 // Accept explicit immediate argument form instead of comparison code.
732 let neverHasSideEffects = 1 in {
733 def rri_alt : PIi8<0xC2, MRMSrcReg,
734 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
735 asm_alt, [], IIC_SSE_ALU_F32P_RR, d>;
736 def rmi_alt : PIi8<0xC2, MRMSrcMem,
737 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
738 asm_alt, [], IIC_SSE_ALU_F32P_RM, d>;
739 }
740}
741
742defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, AVXCC, X86cmpm, v16f32,
743 "vcmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
744 "vcmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
745 SSEPackedSingle>, TB, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VF>;
746defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, AVXCC, X86cmpm, v8f64,
747 "vcmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
748 "vcmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
749 SSEPackedDouble>, TB, OpSize, EVEX_4V, VEX_W, EVEX_V512,
750 EVEX_CD8<64, CD8VF>;
751
752def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
753 (COPY_TO_REGCLASS (VCMPPSZrri
754 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
755 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
756 imm:$cc), VK8)>;
757def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
758 (COPY_TO_REGCLASS (VPCMPDZrri
759 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
760 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
761 imm:$cc), VK8)>;
762def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
763 (COPY_TO_REGCLASS (VPCMPUDZrri
764 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
765 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
766 imm:$cc), VK8)>;
767
768// Mask register copy, including
769// - copy between mask registers
770// - load/store mask registers
771// - copy from GPR to mask register and vice versa
772//
773multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
774 string OpcodeStr, RegisterClass KRC,
775 ValueType vt, X86MemOperand x86memop> {
776 let neverHasSideEffects = 1 in {
777 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
778 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
779 let mayLoad = 1 in
780 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
781 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
782 [(set KRC:$dst, (vt (load addr:$src)))]>;
783 let mayStore = 1 in
784 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
785 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
786 }
787}
788
789multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
790 string OpcodeStr,
791 RegisterClass KRC, RegisterClass GRC> {
792 let neverHasSideEffects = 1 in {
793 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
794 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
795 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
796 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
797 }
798}
799
800let Predicates = [HasAVX512] in {
801 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
802 VEX, TB;
803 defm KMOVW : avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
804 VEX, TB;
805}
806
807let Predicates = [HasAVX512] in {
808 // GR16 from/to 16-bit mask
809 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
810 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
811 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
812 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
813
814 // Store kreg in memory
815 def : Pat<(store (v16i1 VK16:$src), addr:$dst),
816 (KMOVWmk addr:$dst, VK16:$src)>;
817
818 def : Pat<(store (v8i1 VK8:$src), addr:$dst),
819 (KMOVWmk addr:$dst, (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16)))>;
820}
821// With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
822let Predicates = [HasAVX512] in {
823 // GR from/to 8-bit mask without native support
824 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
825 (COPY_TO_REGCLASS
826 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
827 VK8)>;
828 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
829 (EXTRACT_SUBREG
830 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
831 sub_8bit)>;
832}
833
834// Mask unary operation
835// - KNOT
836multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
837 RegisterClass KRC, SDPatternOperator OpNode> {
838 let Predicates = [HasAVX512] in
839 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
840 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
841 [(set KRC:$dst, (OpNode KRC:$src))]>;
842}
843
844multiclass avx512_mask_unop_w<bits<8> opc, string OpcodeStr,
845 SDPatternOperator OpNode> {
846 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
847 VEX, TB;
848}
849
850defm KNOT : avx512_mask_unop_w<0x44, "knot", not>;
851
852def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
853def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
854 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
855
856// With AVX-512, 8-bit mask is promoted to 16-bit mask.
857def : Pat<(not VK8:$src),
858 (COPY_TO_REGCLASS
859 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
860
861// Mask binary operation
862// - KADD, KAND, KANDN, KOR, KXNOR, KXOR
863multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
864 RegisterClass KRC, SDPatternOperator OpNode> {
865 let Predicates = [HasAVX512] in
866 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
867 !strconcat(OpcodeStr,
868 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
869 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
870}
871
872multiclass avx512_mask_binop_w<bits<8> opc, string OpcodeStr,
873 SDPatternOperator OpNode> {
874 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
875 VEX_4V, VEX_L, TB;
876}
877
878def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
879def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
880
881let isCommutable = 1 in {
882 defm KADD : avx512_mask_binop_w<0x4a, "kadd", add>;
883 defm KAND : avx512_mask_binop_w<0x41, "kand", and>;
884 let isCommutable = 0 in
885 defm KANDN : avx512_mask_binop_w<0x42, "kandn", andn>;
886 defm KOR : avx512_mask_binop_w<0x45, "kor", or>;
887 defm KXNOR : avx512_mask_binop_w<0x46, "kxnor", xnor>;
888 defm KXOR : avx512_mask_binop_w<0x47, "kxor", xor>;
889}
890
891multiclass avx512_mask_binop_int<string IntName, string InstName> {
892 let Predicates = [HasAVX512] in
893 def : Pat<(!cast<Intrinsic>("int_x86_"##IntName##"_v16i1")
894 VK16:$src1, VK16:$src2),
895 (!cast<Instruction>(InstName##"Wrr") VK16:$src1, VK16:$src2)>;
896}
897
898defm : avx512_mask_binop_int<"kadd", "KADD">;
899defm : avx512_mask_binop_int<"kand", "KAND">;
900defm : avx512_mask_binop_int<"kandn", "KANDN">;
901defm : avx512_mask_binop_int<"kor", "KOR">;
902defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
903defm : avx512_mask_binop_int<"kxor", "KXOR">;
904// With AVX-512, 8-bit mask is promoted to 16-bit mask.
905multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
906 let Predicates = [HasAVX512] in
907 def : Pat<(OpNode VK8:$src1, VK8:$src2),
908 (COPY_TO_REGCLASS
909 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
910 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
911}
912
913defm : avx512_binop_pat<and, KANDWrr>;
914defm : avx512_binop_pat<andn, KANDNWrr>;
915defm : avx512_binop_pat<or, KORWrr>;
916defm : avx512_binop_pat<xnor, KXNORWrr>;
917defm : avx512_binop_pat<xor, KXORWrr>;
918
919// Mask unpacking
920multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
921 RegisterClass KRC1, RegisterClass KRC2> {
922 let Predicates = [HasAVX512] in
923 def rr : I<opc, MRMSrcReg, (outs KRC1:$dst), (ins KRC2:$src1, KRC2:$src2),
924 !strconcat(OpcodeStr,
925 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
926}
927
928multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
929 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16, VK8>,
930 VEX_4V, VEX_L, OpSize, TB;
931}
932
933defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
934
935multiclass avx512_mask_unpck_int<string IntName, string InstName> {
936 let Predicates = [HasAVX512] in
937 def : Pat<(!cast<Intrinsic>("int_x86_"##IntName##"_v16i1")
938 VK8:$src1, VK8:$src2),
939 (!cast<Instruction>(InstName##"BWrr") VK8:$src1, VK8:$src2)>;
940}
941
942defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
943// Mask bit testing
944multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
945 SDNode OpNode> {
946 let Predicates = [HasAVX512], Defs = [EFLAGS] in
947 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
948 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
949 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
950}
951
952multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
953 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
954 VEX, TB;
955}
956
957defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
958defm KTEST : avx512_mask_testop_w<0x99, "ktest", X86ktest>;
959
960// Mask shift
961multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
962 SDNode OpNode> {
963 let Predicates = [HasAVX512] in
964 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
965 !strconcat(OpcodeStr,
966 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
967 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
968}
969
970multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
971 SDNode OpNode> {
972 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
973 VEX, OpSize, TA, VEX_W;
974}
975
976defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", shl>;
977defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", srl>;
978
979// Mask setting all 0s or 1s
980multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
981 let Predicates = [HasAVX512] in
982 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
983 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
984 [(set KRC:$dst, (VT Val))]>;
985}
986
987multiclass avx512_mask_setop_w<PatFrag Val> {
988 defm B : avx512_mask_setop<VK8, v8i1, Val>;
989 defm W : avx512_mask_setop<VK16, v16i1, Val>;
990}
991
992defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
993defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
994
995// With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
996let Predicates = [HasAVX512] in {
997 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
998 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
999}
1000def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1001 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1002
1003def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1004 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1005
1006def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1007 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1008
1009//===----------------------------------------------------------------------===//
1010// AVX-512 - Aligned and unaligned load and store
1011//
1012
1013multiclass avx512_mov_packed<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1014 X86MemOperand x86memop, PatFrag ld_frag,
1015 string asm, Domain d> {
1016let neverHasSideEffects = 1 in
1017 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1018 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>,
1019 EVEX;
1020let canFoldAsLoad = 1 in
1021 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1022 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1023 [(set RC:$dst, (ld_frag addr:$src))], d>, EVEX;
1024let Constraints = "$src1 = $dst" in {
1025 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1026 (ins RC:$src1, KRC:$mask, RC:$src2),
1027 !strconcat(asm,
1028 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1029 EVEX, EVEX_K;
1030 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1031 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1032 !strconcat(asm,
1033 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1034 [], d>, EVEX, EVEX_K;
1035}
1036}
1037
1038defm VMOVAPSZ : avx512_mov_packed<0x28, VR512, VK16WM, f512mem, alignedloadv16f32,
1039 "vmovaps", SSEPackedSingle>,
1040 EVEX_V512, EVEX_CD8<32, CD8VF>;
1041defm VMOVAPDZ : avx512_mov_packed<0x28, VR512, VK8WM, f512mem, alignedloadv8f64,
1042 "vmovapd", SSEPackedDouble>,
1043 OpSize, EVEX_V512, VEX_W,
1044 EVEX_CD8<64, CD8VF>;
1045defm VMOVUPSZ : avx512_mov_packed<0x10, VR512, VK16WM, f512mem, loadv16f32,
1046 "vmovups", SSEPackedSingle>,
1047 TB, EVEX_V512, EVEX_CD8<32, CD8VF>;
1048defm VMOVUPDZ : avx512_mov_packed<0x10, VR512, VK8WM, f512mem, loadv8f64,
1049 "vmovupd", SSEPackedDouble>,
1050 OpSize, EVEX_V512, VEX_W,
1051 EVEX_CD8<64, CD8VF>;
1052def VMOVAPSZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1053 "vmovaps\t{$src, $dst|$dst, $src}",
1054 [(alignedstore512 (v16f32 VR512:$src), addr:$dst)],
1055 SSEPackedSingle>, EVEX, EVEX_V512, TB,
1056 EVEX_CD8<32, CD8VF>;
1057def VMOVAPDZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1058 "vmovapd\t{$src, $dst|$dst, $src}",
1059 [(alignedstore512 (v8f64 VR512:$src), addr:$dst)],
1060 SSEPackedDouble>, EVEX, EVEX_V512,
1061 OpSize, TB, VEX_W, EVEX_CD8<64, CD8VF>;
1062def VMOVUPSZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1063 "vmovups\t{$src, $dst|$dst, $src}",
1064 [(store (v16f32 VR512:$src), addr:$dst)],
1065 SSEPackedSingle>, EVEX, EVEX_V512, TB,
1066 EVEX_CD8<32, CD8VF>;
1067def VMOVUPDZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1068 "vmovupd\t{$src, $dst|$dst, $src}",
1069 [(store (v8f64 VR512:$src), addr:$dst)],
1070 SSEPackedDouble>, EVEX, EVEX_V512,
1071 OpSize, TB, VEX_W, EVEX_CD8<64, CD8VF>;
1072
1073// Use vmovaps/vmovups for AVX-512 integer load/store.
1074// 512-bit load/store
1075def : Pat<(alignedloadv8i64 addr:$src),
1076 (VMOVAPSZrm addr:$src)>;
1077def : Pat<(loadv8i64 addr:$src),
1078 (VMOVUPSZrm addr:$src)>;
1079
1080def : Pat<(alignedstore512 (v8i64 VR512:$src), addr:$dst),
1081 (VMOVAPSZmr addr:$dst, VR512:$src)>;
1082def : Pat<(alignedstore512 (v16i32 VR512:$src), addr:$dst),
1083 (VMOVAPSZmr addr:$dst, VR512:$src)>;
1084
1085def : Pat<(store (v8i64 VR512:$src), addr:$dst),
1086 (VMOVUPDZmr addr:$dst, VR512:$src)>;
1087def : Pat<(store (v16i32 VR512:$src), addr:$dst),
1088 (VMOVUPSZmr addr:$dst, VR512:$src)>;
1089
1090let neverHasSideEffects = 1 in {
1091 def VMOVDQA32rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1092 (ins VR512:$src),
1093 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1094 EVEX, EVEX_V512;
1095 def VMOVDQA64rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1096 (ins VR512:$src),
1097 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1098 EVEX, EVEX_V512, VEX_W;
1099let mayStore = 1 in {
1100 def VMOVDQA32mr : AVX512BI<0x7F, MRMDestMem, (outs),
1101 (ins i512mem:$dst, VR512:$src),
1102 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1103 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1104 def VMOVDQA64mr : AVX512BI<0x7F, MRMDestMem, (outs),
1105 (ins i512mem:$dst, VR512:$src),
1106 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1107 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1108}
1109let mayLoad = 1 in {
1110def VMOVDQA32rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1111 (ins i512mem:$src),
1112 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1113 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1114def VMOVDQA64rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1115 (ins i512mem:$src),
1116 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1117 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1118}
1119}
1120
1121multiclass avx512_mov_int<bits<8> opc, string asm, RegisterClass RC,
1122 RegisterClass KRC,
1123 PatFrag ld_frag, X86MemOperand x86memop> {
1124let neverHasSideEffects = 1 in
1125 def rr : AVX512XSI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1126 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), []>,
1127 EVEX;
1128let canFoldAsLoad = 1 in
1129 def rm : AVX512XSI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1130 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1131 [(set RC:$dst, (ld_frag addr:$src))]>,
1132 EVEX;
1133let Constraints = "$src1 = $dst" in {
1134 def rrk : AVX512XSI<opc, MRMSrcReg, (outs RC:$dst),
1135 (ins RC:$src1, KRC:$mask, RC:$src2),
1136 !strconcat(asm,
1137 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), []>,
1138 EVEX, EVEX_K;
1139 def rmk : AVX512XSI<opc, MRMSrcMem, (outs RC:$dst),
1140 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1141 !strconcat(asm,
1142 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1143 []>, EVEX, EVEX_K;
1144}
1145}
1146
1147defm VMOVDQU32 : avx512_mov_int<0x6F, "vmovdqu32", VR512, VK16WM, memopv16i32, i512mem>,
1148 EVEX_V512, EVEX_CD8<32, CD8VF>;
1149defm VMOVDQU64 : avx512_mov_int<0x6F, "vmovdqu64", VR512, VK8WM, memopv8i64, i512mem>,
1150 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1151
1152let AddedComplexity = 20 in {
1153def : Pat<(v16f32 (vselect VK16WM:$mask, (v16f32 VR512:$src1),
1154 (v16f32 VR512:$src2))),
1155 (VMOVUPSZrrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1156def : Pat<(v8f64 (vselect VK8WM:$mask, (v8f64 VR512:$src1),
1157 (v8f64 VR512:$src2))),
1158 (VMOVUPDZrrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1159def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src1),
1160 (v16i32 VR512:$src2))),
1161 (VMOVDQU32rrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1162def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src1),
1163 (v8i64 VR512:$src2))),
1164 (VMOVDQU64rrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1165}
1166// Move Int Doubleword to Packed Double Int
1167//
1168def VMOVDI2PDIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
1169 "vmovd{z}\t{$src, $dst|$dst, $src}",
1170 [(set VR128X:$dst,
1171 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
1172 EVEX, VEX_LIG;
1173def VMOVDI2PDIZrm : AVX512SI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
1174 "vmovd{z}\t{$src, $dst|$dst, $src}",
1175 [(set VR128X:$dst,
1176 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
1177 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1178def VMOV64toPQIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
1179 "vmovq{z}\t{$src, $dst|$dst, $src}",
1180 [(set VR128X:$dst,
1181 (v2i64 (scalar_to_vector GR64:$src)))],
1182 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
1183def VMOV64toSDZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1184 "vmovq{z}\t{$src, $dst|$dst, $src}",
1185 [(set FR64:$dst, (bitconvert GR64:$src))],
1186 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1187def VMOVSDto64Zrr : AVX512SI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1188 "vmovq{z}\t{$src, $dst|$dst, $src}",
1189 [(set GR64:$dst, (bitconvert FR64:$src))],
1190 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1191def VMOVSDto64Zmr : AVX512SI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1192 "vmovq{z}\t{$src, $dst|$dst, $src}",
1193 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
1194 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
1195 EVEX_CD8<64, CD8VT1>;
1196
1197// Move Int Doubleword to Single Scalar
1198//
1199def VMOVDI2SSZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
1200 "vmovd{z}\t{$src, $dst|$dst, $src}",
1201 [(set FR32X:$dst, (bitconvert GR32:$src))],
1202 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
1203
1204def VMOVDI2SSZrm : AVX512SI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
1205 "vmovd{z}\t{$src, $dst|$dst, $src}",
1206 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
1207 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1208
1209// Move Packed Doubleword Int to Packed Double Int
1210//
1211def VMOVPDI2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
1212 "vmovd{z}\t{$src, $dst|$dst, $src}",
1213 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
1214 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
1215 EVEX, VEX_LIG;
1216def VMOVPDI2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
1217 (ins i32mem:$dst, VR128X:$src),
1218 "vmovd{z}\t{$src, $dst|$dst, $src}",
1219 [(store (i32 (vector_extract (v4i32 VR128X:$src),
1220 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
1221 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1222
1223// Move Packed Doubleword Int first element to Doubleword Int
1224//
1225def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
1226 "vmovq{z}\t{$src, $dst|$dst, $src}",
1227 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
1228 (iPTR 0)))],
1229 IIC_SSE_MOVD_ToGP>, TB, OpSize, EVEX, VEX_LIG, VEX_W,
1230 Requires<[HasAVX512, In64BitMode]>;
1231
1232def VMOVPQIto64Zmr : I<0x7E, MRMDestMem, (outs),
1233 (ins i64mem:$dst, VR128X:$src),
1234 "vmovq{z}\t{$src, $dst|$dst, $src}",
1235 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
1236 addr:$dst)], IIC_SSE_MOVDQ>,
1237 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
1238 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
1239
1240// Move Scalar Single to Double Int
1241//
1242def VMOVSS2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst),
1243 (ins FR32X:$src),
1244 "vmovd{z}\t{$src, $dst|$dst, $src}",
1245 [(set GR32:$dst, (bitconvert FR32X:$src))],
1246 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
1247def VMOVSS2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
1248 (ins i32mem:$dst, FR32X:$src),
1249 "vmovd{z}\t{$src, $dst|$dst, $src}",
1250 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
1251 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1252
1253// Move Quadword Int to Packed Quadword Int
1254//
1255def VMOVQI2PQIZrm : AVX512SI<0x7E, MRMSrcMem, (outs VR128X:$dst),
1256 (ins i64mem:$src),
1257 "vmovq{z}\t{$src, $dst|$dst, $src}",
1258 [(set VR128X:$dst,
1259 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
1260 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
1261
1262//===----------------------------------------------------------------------===//
1263// AVX-512 MOVSS, MOVSD
1264//===----------------------------------------------------------------------===//
1265
1266multiclass avx512_move_scalar <string asm, RegisterClass RC,
1267 SDNode OpNode, ValueType vt,
1268 X86MemOperand x86memop, PatFrag mem_pat> {
1269 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
1270 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1271 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
1272 (scalar_to_vector RC:$src2))))],
1273 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
1274 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1275 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1276 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
1277 EVEX, VEX_LIG;
1278 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1279 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1280 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
1281 EVEX, VEX_LIG;
1282}
1283
1284let ExeDomain = SSEPackedSingle in
1285defm VMOVSSZ : avx512_move_scalar<"movss{z}", FR32X, X86Movss, v4f32, f32mem,
1286 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
1287
1288let ExeDomain = SSEPackedDouble in
1289defm VMOVSDZ : avx512_move_scalar<"movsd{z}", FR64X, X86Movsd, v2f64, f64mem,
1290 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
1291
1292
1293// For the disassembler
1294let isCodeGenOnly = 1 in {
1295 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1296 (ins VR128X:$src1, FR32X:$src2),
1297 "movss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1298 IIC_SSE_MOV_S_RR>,
1299 XS, EVEX_4V, VEX_LIG;
1300 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1301 (ins VR128X:$src1, FR64X:$src2),
1302 "movsd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1303 IIC_SSE_MOV_S_RR>,
1304 XD, EVEX_4V, VEX_LIG, VEX_W;
1305}
1306
1307let Predicates = [HasAVX512] in {
1308 let AddedComplexity = 15 in {
1309 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
1310 // MOVS{S,D} to the lower bits.
1311 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
1312 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
1313 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
1314 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1315 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
1316 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1317 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
1318 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
1319
1320 // Move low f32 and clear high bits.
1321 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
1322 (SUBREG_TO_REG (i32 0),
1323 (VMOVSSZrr (v4f32 (V_SET0)),
1324 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
1325 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
1326 (SUBREG_TO_REG (i32 0),
1327 (VMOVSSZrr (v4i32 (V_SET0)),
1328 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
1329 }
1330
1331 let AddedComplexity = 20 in {
1332 // MOVSSrm zeros the high parts of the register; represent this
1333 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1334 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
1335 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1336 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
1337 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1338 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1339 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1340
1341 // MOVSDrm zeros the high parts of the register; represent this
1342 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1343 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1344 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1345 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1346 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1347 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1348 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1349 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1350 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1351 def : Pat<(v2f64 (X86vzload addr:$src)),
1352 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1353
1354 // Represent the same patterns above but in the form they appear for
1355 // 256-bit types
1356 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1357 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
1358 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
1359 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1360 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
1361 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
1362 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1363 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
1364 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
1365 }
1366 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1367 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
1368 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
1369 FR32X:$src)), sub_xmm)>;
1370 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1371 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
1372 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
1373 FR64X:$src)), sub_xmm)>;
1374 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1375 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
1376 (SUBREG_TO_REG (i64 0), (VMOVSDZrm addr:$src), sub_xmm)>;
1377
1378 // Move low f64 and clear high bits.
1379 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
1380 (SUBREG_TO_REG (i32 0),
1381 (VMOVSDZrr (v2f64 (V_SET0)),
1382 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
1383
1384 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
1385 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
1386 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
1387
1388 // Extract and store.
1389 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
1390 addr:$dst),
1391 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
1392 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
1393 addr:$dst),
1394 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
1395
1396 // Shuffle with VMOVSS
1397 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
1398 (VMOVSSZrr (v4i32 VR128X:$src1),
1399 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
1400 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
1401 (VMOVSSZrr (v4f32 VR128X:$src1),
1402 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
1403
1404 // 256-bit variants
1405 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
1406 (SUBREG_TO_REG (i32 0),
1407 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
1408 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
1409 sub_xmm)>;
1410 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
1411 (SUBREG_TO_REG (i32 0),
1412 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
1413 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
1414 sub_xmm)>;
1415
1416 // Shuffle with VMOVSD
1417 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1418 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1419 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1420 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1421 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1422 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1423 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1424 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1425
1426 // 256-bit variants
1427 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1428 (SUBREG_TO_REG (i32 0),
1429 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
1430 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
1431 sub_xmm)>;
1432 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1433 (SUBREG_TO_REG (i32 0),
1434 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
1435 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
1436 sub_xmm)>;
1437
1438 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1439 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1440 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1441 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1442 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1443 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1444 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1445 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1446}
1447
1448let AddedComplexity = 15 in
1449def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
1450 (ins VR128X:$src),
1451 "vmovq{z}\t{$src, $dst|$dst, $src}",
1452 [(set VR128X:$dst, (v2i64 (X86vzmovl
1453 (v2i64 VR128X:$src))))],
1454 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
1455
1456let AddedComplexity = 20 in
1457def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
1458 (ins i128mem:$src),
1459 "vmovq{z}\t{$src, $dst|$dst, $src}",
1460 [(set VR128X:$dst, (v2i64 (X86vzmovl
1461 (loadv2i64 addr:$src))))],
1462 IIC_SSE_MOVDQ>, EVEX, VEX_W,
1463 EVEX_CD8<8, CD8VT8>;
1464
1465let Predicates = [HasAVX512] in {
1466 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
1467 let AddedComplexity = 20 in {
1468 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
1469 (VMOVDI2PDIZrm addr:$src)>;
1470
1471 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
1472 (VMOVDI2PDIZrm addr:$src)>;
1473 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
1474 (VMOVDI2PDIZrm addr:$src)>;
1475 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
1476 (VMOVZPQILo2PQIZrm addr:$src)>;
1477 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
1478 (VMOVZPQILo2PQIZrr VR128X:$src)>;
1479 }
1480 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
1481 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1482 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
1483 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
1484 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1485 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
1486 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
1487}
1488
1489def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
1490 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1491
1492def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
1493 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1494
1495def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
1496 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1497
1498def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
1499 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1500
1501//===----------------------------------------------------------------------===//
1502// AVX-512 - Integer arithmetic
1503//
1504multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1505 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1506 X86MemOperand x86memop, PatFrag scalar_mfrag,
1507 X86MemOperand x86scalar_mop, string BrdcstStr,
1508 OpndItins itins, bit IsCommutable = 0> {
1509 let isCommutable = IsCommutable in
1510 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1511 (ins RC:$src1, RC:$src2),
1512 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1513 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1514 itins.rr>, EVEX_4V;
1515 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1516 (ins RC:$src1, x86memop:$src2),
1517 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1518 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
1519 itins.rm>, EVEX_4V;
1520 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1521 (ins RC:$src1, x86scalar_mop:$src2),
1522 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
1523 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1524 [(set RC:$dst, (OpNode RC:$src1,
1525 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1526 itins.rm>, EVEX_4V, EVEX_B;
1527}
1528multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr,
1529 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
1530 PatFrag memop_frag, X86MemOperand x86memop,
1531 OpndItins itins,
1532 bit IsCommutable = 0> {
1533 let isCommutable = IsCommutable in
1534 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1535 (ins RC:$src1, RC:$src2),
1536 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1537 []>, EVEX_4V, VEX_W;
1538 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1539 (ins RC:$src1, x86memop:$src2),
1540 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1541 []>, EVEX_4V, VEX_W;
1542}
1543
1544defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VR512, memopv16i32,
1545 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1546 EVEX_V512, EVEX_CD8<32, CD8VF>;
1547
1548defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VR512, memopv16i32,
1549 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 0>,
1550 EVEX_V512, EVEX_CD8<32, CD8VF>;
1551
1552defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VR512, memopv16i32,
1553 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1554 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1555
1556defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VR512, memopv8i64,
1557 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 1>,
1558 EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
1559
1560defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VR512, memopv8i64,
1561 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1562 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1563
1564defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32,
1565 VR512, memopv8i64, i512mem, SSE_INTALU_ITINS_P, 1>, T8,
1566 EVEX_V512, EVEX_CD8<64, CD8VF>;
1567
1568defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32,
1569 VR512, memopv8i64, i512mem, SSE_INTMUL_ITINS_P, 1>, EVEX_V512,
1570 EVEX_CD8<64, CD8VF>;
1571
1572def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
1573 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
1574
1575//===----------------------------------------------------------------------===//
1576// AVX-512 - Unpack Instructions
1577//===----------------------------------------------------------------------===//
1578
1579multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
1580 PatFrag mem_frag, RegisterClass RC,
1581 X86MemOperand x86memop, string asm,
1582 Domain d> {
1583 def rr : AVX512PI<opc, MRMSrcReg,
1584 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1585 asm, [(set RC:$dst,
1586 (vt (OpNode RC:$src1, RC:$src2)))],
1587 d>, EVEX_4V, TB;
1588 def rm : AVX512PI<opc, MRMSrcMem,
1589 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1590 asm, [(set RC:$dst,
1591 (vt (OpNode RC:$src1,
1592 (bitconvert (mem_frag addr:$src2)))))],
1593 d>, EVEX_4V, TB;
1594}
1595
1596defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
1597 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1598 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1599defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
1600 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1601 SSEPackedDouble>, OpSize, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1602defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
1603 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1604 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1605defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
1606 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1607 SSEPackedDouble>, OpSize, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1608
1609multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
1610 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1611 X86MemOperand x86memop> {
1612 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1613 (ins RC:$src1, RC:$src2),
1614 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1615 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1616 IIC_SSE_UNPCK>, EVEX_4V;
1617 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1618 (ins RC:$src1, x86memop:$src2),
1619 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1620 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
1621 (bitconvert (memop_frag addr:$src2)))))],
1622 IIC_SSE_UNPCK>, EVEX_4V;
1623}
1624defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
1625 VR512, memopv16i32, i512mem>, EVEX_V512,
1626 EVEX_CD8<32, CD8VF>;
1627defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
1628 VR512, memopv8i64, i512mem>, EVEX_V512,
1629 VEX_W, EVEX_CD8<64, CD8VF>;
1630defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
1631 VR512, memopv16i32, i512mem>, EVEX_V512,
1632 EVEX_CD8<32, CD8VF>;
1633defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
1634 VR512, memopv8i64, i512mem>, EVEX_V512,
1635 VEX_W, EVEX_CD8<64, CD8VF>;
1636//===----------------------------------------------------------------------===//
1637// AVX-512 - PSHUFD
1638//
1639
1640multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
1641 SDNode OpNode, PatFrag mem_frag,
1642 X86MemOperand x86memop, ValueType OpVT> {
1643 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
1644 (ins RC:$src1, i8imm:$src2),
1645 !strconcat(OpcodeStr,
1646 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1647 [(set RC:$dst,
1648 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
1649 EVEX;
1650 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
1651 (ins x86memop:$src1, i8imm:$src2),
1652 !strconcat(OpcodeStr,
1653 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1654 [(set RC:$dst,
1655 (OpVT (OpNode (mem_frag addr:$src1),
1656 (i8 imm:$src2))))]>, EVEX;
1657}
1658
1659defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
1660 i512mem, v16i32>, OpSize, EVEX_V512, EVEX_CD8<32, CD8VF>;
1661
1662let ExeDomain = SSEPackedSingle in
1663defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilp,
1664 memopv16f32, i512mem, v16f32>, OpSize, TA, EVEX_V512,
1665 EVEX_CD8<32, CD8VF>;
1666let ExeDomain = SSEPackedDouble in
1667defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilp,
1668 memopv8f64, i512mem, v8f64>, OpSize, TA, EVEX_V512,
1669 VEX_W, EVEX_CD8<32, CD8VF>;
1670
1671def : Pat<(v16i32 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1672 (VPERMILPSZri VR512:$src1, imm:$imm)>;
1673def : Pat<(v8i64 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1674 (VPERMILPDZri VR512:$src1, imm:$imm)>;
1675
1676//===----------------------------------------------------------------------===//
1677// AVX-512 Logical Instructions
1678//===----------------------------------------------------------------------===//
1679
1680defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VR512, memopv16i32,
1681 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1682 EVEX_V512, EVEX_CD8<32, CD8VF>;
1683defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VR512, memopv8i64,
1684 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1685 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1686defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VR512, memopv16i32,
1687 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1688 EVEX_V512, EVEX_CD8<32, CD8VF>;
1689defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VR512, memopv8i64,
1690 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1691 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1692defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VR512, memopv16i32,
1693 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1694 EVEX_V512, EVEX_CD8<32, CD8VF>;
1695defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VR512, memopv8i64,
1696 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1697 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1698defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VR512,
1699 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
1700 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1701defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VR512, memopv8i64,
1702 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 0>,
1703 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1704
1705//===----------------------------------------------------------------------===//
1706// AVX-512 FP arithmetic
1707//===----------------------------------------------------------------------===//
1708
1709multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
1710 SizeItins itins> {
1711 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss{z}"), OpNode, FR32X,
1712 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
1713 EVEX_CD8<32, CD8VT1>;
1714 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd{z}"), OpNode, FR64X,
1715 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
1716 EVEX_CD8<64, CD8VT1>;
1717}
1718
1719let isCommutable = 1 in {
1720defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
1721defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
1722defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
1723defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
1724}
1725let isCommutable = 0 in {
1726defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
1727defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
1728}
1729
1730multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1731 RegisterClass RC, ValueType vt,
1732 X86MemOperand x86memop, PatFrag mem_frag,
1733 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
1734 string BrdcstStr,
1735 Domain d, OpndItins itins, bit commutable> {
1736 let isCommutable = commutable in
1737 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1738 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1739 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
1740 EVEX_4V;
1741 let mayLoad = 1 in {
1742 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1743 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1744 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
1745 itins.rm, d>, EVEX_4V;
1746 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
1747 (ins RC:$src1, x86scalar_mop:$src2),
1748 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
1749 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1750 [(set RC:$dst, (OpNode RC:$src1,
1751 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1752 itins.rm, d>, EVEX_4V, EVEX_B;
1753 }
1754}
1755
1756defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VR512, v16f32, f512mem,
1757 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1758 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1759
1760defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VR512, v8f64, f512mem,
1761 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1762 SSE_ALU_ITINS_P.d, 1>,
1763 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1764
1765defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VR512, v16f32, f512mem,
1766 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1767 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1768defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VR512, v8f64, f512mem,
1769 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1770 SSE_ALU_ITINS_P.d, 1>,
1771 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1772
1773defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VR512, v16f32, f512mem,
1774 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1775 SSE_ALU_ITINS_P.s, 1>,
1776 EVEX_V512, EVEX_CD8<32, CD8VF>;
1777defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VR512, v16f32, f512mem,
1778 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1779 SSE_ALU_ITINS_P.s, 1>,
1780 EVEX_V512, EVEX_CD8<32, CD8VF>;
1781
1782defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VR512, v8f64, f512mem,
1783 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1784 SSE_ALU_ITINS_P.d, 1>,
1785 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1786defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VR512, v8f64, f512mem,
1787 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1788 SSE_ALU_ITINS_P.d, 1>,
1789 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1790
1791defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VR512, v16f32, f512mem,
1792 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1793 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1794defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VR512, v16f32, f512mem,
1795 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1796 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1797
1798defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VR512, v8f64, f512mem,
1799 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1800 SSE_ALU_ITINS_P.d, 0>,
1801 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1802defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VR512, v8f64, f512mem,
1803 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1804 SSE_ALU_ITINS_P.d, 0>,
1805 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1806
1807//===----------------------------------------------------------------------===//
1808// AVX-512 VPTESTM instructions
1809//===----------------------------------------------------------------------===//
1810
1811multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1812 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
1813 SDNode OpNode, ValueType vt> {
1814 def rr : AVX5128I<opc, MRMSrcReg,
1815 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
1816 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1817 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))]>, EVEX_4V;
1818 def rm : AVX5128I<opc, MRMSrcMem,
1819 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
1820 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1821 [(set KRC:$dst, (OpNode (vt RC:$src1),
1822 (bitconvert (memop_frag addr:$src2))))]>, EVEX_4V;
1823}
1824
1825defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
1826 memopv16i32, X86testm, v16i32>, EVEX_V512,
1827 EVEX_CD8<32, CD8VF>;
1828defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
1829 memopv8i64, X86testm, v8i64>, EVEX_V512, VEX_W,
1830 EVEX_CD8<64, CD8VF>;
1831
1832//===----------------------------------------------------------------------===//
1833// AVX-512 Shift instructions
1834//===----------------------------------------------------------------------===//
1835multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
1836 string OpcodeStr, SDNode OpNode, RegisterClass RC,
1837 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
1838 RegisterClass KRC> {
1839 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
1840 (ins RC:$src1, i32i8imm:$src2),
1841 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1842 [(set RC:$dst, (vt (OpNode RC:$src1, (i32 imm:$src2))))],
1843 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
1844 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
1845 (ins KRC:$mask, RC:$src1, i32i8imm:$src2),
1846 !strconcat(OpcodeStr,
1847 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1848 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
1849 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
1850 (ins x86memop:$src1, i32i8imm:$src2),
1851 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1852 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
1853 (i32 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
1854 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
1855 (ins KRC:$mask, x86memop:$src1, i32i8imm:$src2),
1856 !strconcat(OpcodeStr,
1857 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1858 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
1859}
1860
1861multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1862 RegisterClass RC, ValueType vt, ValueType SrcVT,
1863 PatFrag bc_frag, RegisterClass KRC> {
1864 // src2 is always 128-bit
1865 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1866 (ins RC:$src1, VR128X:$src2),
1867 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1868 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
1869 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
1870 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1871 (ins KRC:$mask, RC:$src1, VR128X:$src2),
1872 !strconcat(OpcodeStr,
1873 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1874 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
1875 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1876 (ins RC:$src1, i128mem:$src2),
1877 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1878 [(set RC:$dst, (vt (OpNode RC:$src1,
1879 (bc_frag (memopv2i64 addr:$src2)))))],
1880 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
1881 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1882 (ins KRC:$mask, RC:$src1, i128mem:$src2),
1883 !strconcat(OpcodeStr,
1884 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1885 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
1886}
1887
1888defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
1889 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
1890 EVEX_V512, EVEX_CD8<32, CD8VF>;
1891defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
1892 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
1893 EVEX_CD8<32, CD8VQ>;
1894
1895defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
1896 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
1897 EVEX_CD8<64, CD8VF>, VEX_W;
1898defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
1899 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
1900 EVEX_CD8<64, CD8VQ>, VEX_W;
1901
1902defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
1903 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
1904 EVEX_CD8<32, CD8VF>;
1905defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
1906 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
1907 EVEX_CD8<32, CD8VQ>;
1908
1909defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
1910 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
1911 EVEX_CD8<64, CD8VF>, VEX_W;
1912defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
1913 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
1914 EVEX_CD8<64, CD8VQ>, VEX_W;
1915
1916defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
1917 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
1918 EVEX_V512, EVEX_CD8<32, CD8VF>;
1919defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
1920 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
1921 EVEX_CD8<32, CD8VQ>;
1922
1923defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
1924 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
1925 EVEX_CD8<64, CD8VF>, VEX_W;
1926defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
1927 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
1928 EVEX_CD8<64, CD8VQ>, VEX_W;
1929
1930//===-------------------------------------------------------------------===//
1931// Variable Bit Shifts
1932//===-------------------------------------------------------------------===//
1933multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
1934 RegisterClass RC, ValueType vt,
1935 X86MemOperand x86memop, PatFrag mem_frag> {
1936 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
1937 (ins RC:$src1, RC:$src2),
1938 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1939 [(set RC:$dst,
1940 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
1941 EVEX_4V;
1942 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1943 (ins RC:$src1, x86memop:$src2),
1944 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1945 [(set RC:$dst,
1946 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
1947 EVEX_4V;
1948}
1949
1950defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
1951 i512mem, memopv16i32>, EVEX_V512,
1952 EVEX_CD8<32, CD8VF>;
1953defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
1954 i512mem, memopv8i64>, EVEX_V512, VEX_W,
1955 EVEX_CD8<64, CD8VF>;
1956defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
1957 i512mem, memopv16i32>, EVEX_V512,
1958 EVEX_CD8<32, CD8VF>;
1959defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
1960 i512mem, memopv8i64>, EVEX_V512, VEX_W,
1961 EVEX_CD8<64, CD8VF>;
1962defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
1963 i512mem, memopv16i32>, EVEX_V512,
1964 EVEX_CD8<32, CD8VF>;
1965defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
1966 i512mem, memopv8i64>, EVEX_V512, VEX_W,
1967 EVEX_CD8<64, CD8VF>;
1968
1969//===----------------------------------------------------------------------===//
1970// AVX-512 - MOVDDUP
1971//===----------------------------------------------------------------------===//
1972
1973multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
1974 X86MemOperand x86memop, PatFrag memop_frag> {
1975def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1976 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1977 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
1978def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1979 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1980 [(set RC:$dst,
1981 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
1982}
1983
1984defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
1985 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
1986def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
1987 (VMOVDDUPZrm addr:$src)>;
1988
1989def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
1990 (ins VR128X:$src1, VR128X:$src2),
1991 "vmovlhps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1992 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
1993 IIC_SSE_MOV_LH>, EVEX_4V;
1994def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
1995 (ins VR128X:$src1, VR128X:$src2),
1996 "vmovhlps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1997 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
1998 IIC_SSE_MOV_LH>, EVEX_4V;
1999
2000// MOVLHPS patterns
2001def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2002 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
2003def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2004 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
2005
2006// MOVHLPS patterns
2007def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
2008 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
2009
2010//===----------------------------------------------------------------------===//
2011// FMA - Fused Multiply Operations
2012//
2013let Constraints = "$src1 = $dst" in {
2014multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
2015 RegisterClass RC, X86MemOperand x86memop,
2016 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2017 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2018 def r: AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2019 (ins RC:$src1, RC:$src2, RC:$src3),
2020 !strconcat(OpcodeStr,"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2021 [(set RC:$dst, (OpVT(OpNode RC:$src1, RC:$src2, RC:$src3)))]>;
2022
2023 let mayLoad = 1 in
2024 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2025 (ins RC:$src1, RC:$src2, x86memop:$src3),
2026 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2027 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2,
2028 (mem_frag addr:$src3))))]>;
2029 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2030 (ins RC:$src1, RC:$src2, x86scalar_mop:$src3),
2031 !strconcat(OpcodeStr, "\t{${src3}", BrdcstStr,
2032 ", $src2, $dst|$dst, $src2, ${src3}", BrdcstStr, "}"),
2033 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
2034 (OpVT (X86VBroadcast (scalar_mfrag addr:$src3)))))]>, EVEX_B;
2035}
2036} // Constraints = "$src1 = $dst"
2037
2038let ExeDomain = SSEPackedSingle in {
2039 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem,
2040 memopv16f32, f32mem, loadf32, "{1to16}",
2041 X86Fmadd, v16f32>, EVEX_V512,
2042 EVEX_CD8<32, CD8VF>;
2043 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem,
2044 memopv16f32, f32mem, loadf32, "{1to16}",
2045 X86Fmsub, v16f32>, EVEX_V512,
2046 EVEX_CD8<32, CD8VF>;
2047 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem,
2048 memopv16f32, f32mem, loadf32, "{1to16}",
2049 X86Fmaddsub, v16f32>,
2050 EVEX_V512, EVEX_CD8<32, CD8VF>;
2051 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem,
2052 memopv16f32, f32mem, loadf32, "{1to16}",
2053 X86Fmsubadd, v16f32>,
2054 EVEX_V512, EVEX_CD8<32, CD8VF>;
2055 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem,
2056 memopv16f32, f32mem, loadf32, "{1to16}",
2057 X86Fnmadd, v16f32>, EVEX_V512,
2058 EVEX_CD8<32, CD8VF>;
2059 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem,
2060 memopv16f32, f32mem, loadf32, "{1to16}",
2061 X86Fnmsub, v16f32>, EVEX_V512,
2062 EVEX_CD8<32, CD8VF>;
2063}
2064let ExeDomain = SSEPackedDouble in {
2065 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem,
2066 memopv8f64, f64mem, loadf64, "{1to8}",
2067 X86Fmadd, v8f64>, EVEX_V512,
2068 VEX_W, EVEX_CD8<64, CD8VF>;
2069 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem,
2070 memopv8f64, f64mem, loadf64, "{1to8}",
2071 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2072 EVEX_CD8<64, CD8VF>;
2073 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem,
2074 memopv8f64, f64mem, loadf64, "{1to8}",
2075 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2076 EVEX_CD8<64, CD8VF>;
2077 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem,
2078 memopv8f64, f64mem, loadf64, "{1to8}",
2079 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2080 EVEX_CD8<64, CD8VF>;
2081 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem,
2082 memopv8f64, f64mem, loadf64, "{1to8}",
2083 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2084 EVEX_CD8<64, CD8VF>;
2085 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem,
2086 memopv8f64, f64mem, loadf64, "{1to8}",
2087 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2088 EVEX_CD8<64, CD8VF>;
2089}
2090
2091let Constraints = "$src1 = $dst" in {
2092multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr,
2093 RegisterClass RC, X86MemOperand x86memop,
2094 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2095 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2096 let mayLoad = 1 in
2097 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2098 (ins RC:$src1, RC:$src3, x86memop:$src2),
2099 !strconcat(OpcodeStr, "\t{$src2, $src3, $dst|$dst, $src3, $src2}"),
2100 [(set RC:$dst, (OpVT (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3)))]>;
2101 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2102 (ins RC:$src1, RC:$src3, x86scalar_mop:$src2),
2103 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
2104 ", $src3, $dst|$dst, $src3, ${src2}", BrdcstStr, "}"),
2105 [(set RC:$dst, (OpNode RC:$src1,
2106 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2))), RC:$src3))]>, EVEX_B;
2107}
2108} // Constraints = "$src1 = $dst"
2109
2110
2111let ExeDomain = SSEPackedSingle in {
2112 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", VR512, f512mem,
2113 memopv16f32, f32mem, loadf32, "{1to16}",
2114 X86Fmadd, v16f32>, EVEX_V512,
2115 EVEX_CD8<32, CD8VF>;
2116 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", VR512, f512mem,
2117 memopv16f32, f32mem, loadf32, "{1to16}",
2118 X86Fmsub, v16f32>, EVEX_V512,
2119 EVEX_CD8<32, CD8VF>;
2120 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", VR512, f512mem,
2121 memopv16f32, f32mem, loadf32, "{1to16}",
2122 X86Fmaddsub, v16f32>,
2123 EVEX_V512, EVEX_CD8<32, CD8VF>;
2124 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", VR512, f512mem,
2125 memopv16f32, f32mem, loadf32, "{1to16}",
2126 X86Fmsubadd, v16f32>,
2127 EVEX_V512, EVEX_CD8<32, CD8VF>;
2128 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", VR512, f512mem,
2129 memopv16f32, f32mem, loadf32, "{1to16}",
2130 X86Fnmadd, v16f32>, EVEX_V512,
2131 EVEX_CD8<32, CD8VF>;
2132 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", VR512, f512mem,
2133 memopv16f32, f32mem, loadf32, "{1to16}",
2134 X86Fnmsub, v16f32>, EVEX_V512,
2135 EVEX_CD8<32, CD8VF>;
2136}
2137let ExeDomain = SSEPackedDouble in {
2138 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", VR512, f512mem,
2139 memopv8f64, f64mem, loadf64, "{1to8}",
2140 X86Fmadd, v8f64>, EVEX_V512,
2141 VEX_W, EVEX_CD8<64, CD8VF>;
2142 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", VR512, f512mem,
2143 memopv8f64, f64mem, loadf64, "{1to8}",
2144 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2145 EVEX_CD8<64, CD8VF>;
2146 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", VR512, f512mem,
2147 memopv8f64, f64mem, loadf64, "{1to8}",
2148 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2149 EVEX_CD8<64, CD8VF>;
2150 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", VR512, f512mem,
2151 memopv8f64, f64mem, loadf64, "{1to8}",
2152 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2153 EVEX_CD8<64, CD8VF>;
2154 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", VR512, f512mem,
2155 memopv8f64, f64mem, loadf64, "{1to8}",
2156 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2157 EVEX_CD8<64, CD8VF>;
2158 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", VR512, f512mem,
2159 memopv8f64, f64mem, loadf64, "{1to8}",
2160 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2161 EVEX_CD8<64, CD8VF>;
2162}
2163
2164// Scalar FMA
2165let Constraints = "$src1 = $dst" in {
2166multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2167 RegisterClass RC, ValueType OpVT,
2168 X86MemOperand x86memop, Operand memop,
2169 PatFrag mem_frag> {
2170 let isCommutable = 1 in
2171 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2172 (ins RC:$src1, RC:$src2, RC:$src3),
2173 !strconcat(OpcodeStr,
2174 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2175 [(set RC:$dst,
2176 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
2177 let mayLoad = 1 in
2178 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2179 (ins RC:$src1, RC:$src2, f128mem:$src3),
2180 !strconcat(OpcodeStr,
2181 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2182 [(set RC:$dst,
2183 (OpVT (OpNode RC:$src2, RC:$src1,
2184 (mem_frag addr:$src3))))]>;
2185}
2186
2187} // Constraints = "$src1 = $dst"
2188
2189defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss{z}", X86Fmadd, FR32X,
2190 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2191defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd{z}", X86Fmadd, FR64X,
2192 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2193defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss{z}", X86Fmsub, FR32X,
2194 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2195defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd{z}", X86Fmsub, FR64X,
2196 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2197defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss{z}", X86Fnmadd, FR32X,
2198 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2199defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd{z}", X86Fnmadd, FR64X,
2200 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2201defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss{z}", X86Fnmsub, FR32X,
2202 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2203defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd{z}", X86Fnmsub, FR64X,
2204 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2205
2206//===----------------------------------------------------------------------===//
2207// AVX-512 Scalar convert from sign integer to float/double
2208//===----------------------------------------------------------------------===//
2209
2210multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2211 X86MemOperand x86memop, string asm> {
2212let neverHasSideEffects = 1 in {
2213 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
2214 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>, EVEX_4V;
2215 let mayLoad = 1 in
2216 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
2217 (ins DstRC:$src1, x86memop:$src),
2218 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>, EVEX_4V;
2219} // neverHasSideEffects = 1
2220}
2221
2222defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}{z}">,
2223 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2224defm VCVTSI2SS64Z : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}{z}">,
2225 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2226defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}{z}">,
2227 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2228defm VCVTSI2SD64Z : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}{z}">,
2229 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2230
2231def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
2232 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2233def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
2234 (VCVTSI2SS64Zrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2235def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
2236 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2237def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
2238 (VCVTSI2SD64Zrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2239
2240def : Pat<(f32 (sint_to_fp GR32:$src)),
2241 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2242def : Pat<(f32 (sint_to_fp GR64:$src)),
2243 (VCVTSI2SS64Zrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2244def : Pat<(f64 (sint_to_fp GR32:$src)),
2245 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2246def : Pat<(f64 (sint_to_fp GR64:$src)),
2247 (VCVTSI2SD64Zrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2248
2249
2250//===----------------------------------------------------------------------===//
2251// AVX-512 Convert form float to double and back
2252//===----------------------------------------------------------------------===//
2253let neverHasSideEffects = 1 in {
2254def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
2255 (ins FR32X:$src1, FR32X:$src2),
2256 "vcvtss2sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2257 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
2258let mayLoad = 1 in
2259def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
2260 (ins FR32X:$src1, f32mem:$src2),
2261 "vcvtss2sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2262 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
2263 EVEX_CD8<32, CD8VT1>;
2264
2265// Convert scalar double to scalar single
2266def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
2267 (ins FR64X:$src1, FR64X:$src2),
2268 "vcvtsd2ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2269 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
2270let mayLoad = 1 in
2271def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
2272 (ins FR64X:$src1, f64mem:$src2),
2273 "vcvtsd2ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2274 []>, EVEX_4V, VEX_LIG, VEX_W,
2275 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
2276}
2277
2278def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
2279 Requires<[HasAVX512]>;
2280def : Pat<(fextend (loadf32 addr:$src)),
2281 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
2282
2283def : Pat<(extloadf32 addr:$src),
2284 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
2285 Requires<[HasAVX512, OptForSize]>;
2286
2287def : Pat<(extloadf32 addr:$src),
2288 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
2289 Requires<[HasAVX512, OptForSpeed]>;
2290
2291def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
2292 Requires<[HasAVX512]>;
2293
2294multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
2295 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
2296 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
2297 Domain d> {
2298let neverHasSideEffects = 1 in {
2299 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2300 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2301 [(set DstRC:$dst,
2302 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
2303 let mayLoad = 1 in
2304 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2305 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2306 [(set DstRC:$dst,
2307 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
2308} // neverHasSideEffects = 1
2309}
2310
2311defm VCVTPD2PSZ : avx512_vcvt_fp<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
2312 memopv8f64, f512mem, v8f32, v8f64,
2313 SSEPackedSingle>, EVEX_V512, VEX_W, OpSize,
2314 EVEX_CD8<64, CD8VF>;
2315
2316defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
2317 memopv4f64, f256mem, v8f64, v8f32,
2318 SSEPackedDouble>, EVEX_V512, EVEX_CD8<32, CD8VH>;
2319def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2320 (VCVTPS2PDZrm addr:$src)>;
2321
2322//===----------------------------------------------------------------------===//
2323// AVX-512 Vector convert from sign integer to float/double
2324//===----------------------------------------------------------------------===//
2325
2326defm VCVTDQ2PSZ : avx512_vcvt_fp<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
2327 memopv8i64, i512mem, v16f32, v16i32,
2328 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2329
2330defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
2331 memopv4i64, i256mem, v8f64, v8i32,
2332 SSEPackedDouble>, EVEX_V512, XS,
2333 EVEX_CD8<32, CD8VH>;
2334
2335defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
2336 memopv16f32, f512mem, v16i32, v16f32,
2337 SSEPackedSingle>, EVEX_V512, XS,
2338 EVEX_CD8<32, CD8VF>;
2339
2340defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
2341 memopv8f64, f512mem, v8i32, v8f64,
2342 SSEPackedDouble>, EVEX_V512, OpSize, VEX_W,
2343 EVEX_CD8<64, CD8VF>;
2344
2345defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
2346 memopv16f32, f512mem, v16i32, v16f32,
2347 SSEPackedSingle>, EVEX_V512,
2348 EVEX_CD8<32, CD8VF>;
2349
2350defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
2351 memopv8f64, f512mem, v8i32, v8f64,
2352 SSEPackedDouble>, EVEX_V512, VEX_W,
2353 EVEX_CD8<64, CD8VF>;
2354
2355defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
2356 memopv4i64, f256mem, v8f64, v8i32,
2357 SSEPackedDouble>, EVEX_V512, XS,
2358 EVEX_CD8<32, CD8VH>;
2359
2360defm VCVTUDQ2PSZ : avx512_vcvt_fp<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
2361 memopv16i32, f512mem, v16f32, v16i32,
2362 SSEPackedSingle>, EVEX_V512, XD,
2363 EVEX_CD8<32, CD8VF>;
2364
2365def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
2366 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
2367 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
2368
2369
2370def : Pat<(int_x86_avx512_cvtdq2_ps_512 VR512:$src),
2371 (VCVTDQ2PSZrr VR512:$src)>;
2372def : Pat<(int_x86_avx512_cvtdq2_ps_512 (bitconvert (memopv8i64 addr:$src))),
2373 (VCVTDQ2PSZrm addr:$src)>;
2374
2375def VCVTPS2DQZrr : AVX512BI<0x5B, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2376 "vcvtps2dq\t{$src, $dst|$dst, $src}",
2377 [(set VR512:$dst,
2378 (int_x86_avx512_cvt_ps2dq_512 VR512:$src))],
2379 IIC_SSE_CVT_PS_RR>, EVEX, EVEX_V512;
2380def VCVTPS2DQZrm : AVX512BI<0x5B, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2381 "vcvtps2dq\t{$src, $dst|$dst, $src}",
2382 [(set VR512:$dst,
2383 (int_x86_avx512_cvt_ps2dq_512 (memopv16f32 addr:$src)))],
2384 IIC_SSE_CVT_PS_RM>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2385
2386
2387let Predicates = [HasAVX512] in {
2388 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
2389 (VCVTPD2PSZrm addr:$src)>;
2390 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2391 (VCVTPS2PDZrm addr:$src)>;
2392}
2393
2394let Defs = [EFLAGS], Predicates = [HasAVX512] in {
2395 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
2396 "ucomiss{z}">, TB, EVEX, VEX_LIG,
2397 EVEX_CD8<32, CD8VT1>;
2398 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
2399 "ucomisd{z}">, TB, OpSize, EVEX,
2400 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2401 let Pattern = []<dag> in {
2402 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
2403 "comiss{z}">, TB, EVEX, VEX_LIG,
2404 EVEX_CD8<32, CD8VT1>;
2405 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
2406 "comisd{z}">, TB, OpSize, EVEX,
2407 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2408 }
2409 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
2410 load, "ucomiss">, TB, EVEX, VEX_LIG,
2411 EVEX_CD8<32, CD8VT1>;
2412 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
2413 load, "ucomisd">, TB, OpSize, EVEX,
2414 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2415
2416 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
2417 load, "comiss">, TB, EVEX, VEX_LIG,
2418 EVEX_CD8<32, CD8VT1>;
2419 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
2420 load, "comisd">, TB, OpSize, EVEX,
2421 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2422}
2423
2424/// avx512_unop_p - AVX-512 unops in packed form.
2425multiclass avx512_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2426 def PSZr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2427 !strconcat(OpcodeStr,
2428 "ps\t{$src, $dst|$dst, $src}"),
2429 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))]>,
2430 EVEX, EVEX_V512;
2431 def PSZm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f256mem:$src),
2432 !strconcat(OpcodeStr,
2433 "ps\t{$src, $dst|$dst, $src}"),
2434 [(set VR512:$dst, (OpNode (memopv16f32 addr:$src)))]>,
2435 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2436 def PDZr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2437 !strconcat(OpcodeStr,
2438 "pd\t{$src, $dst|$dst, $src}"),
2439 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))]>,
2440 EVEX, EVEX_V512, VEX_W;
2441 def PDZm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2442 !strconcat(OpcodeStr,
2443 "pd\t{$src, $dst|$dst, $src}"),
2444 [(set VR512:$dst, (OpNode (memopv16f32 addr:$src)))]>,
2445 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2446}
2447
2448/// avx512_fp_unop_p_int - AVX-512 intrinsics unops in packed forms.
2449multiclass avx512_fp_unop_p_int<bits<8> opc, string OpcodeStr,
2450 Intrinsic V16F32Int, Intrinsic V8F64Int> {
2451 def PSZr_Int : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2452 !strconcat(OpcodeStr,
2453 "ps\t{$src, $dst|$dst, $src}"),
2454 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
2455 EVEX, EVEX_V512;
2456 def PSZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2457 !strconcat(OpcodeStr,
2458 "ps\t{$src, $dst|$dst, $src}"),
2459 [(set VR512:$dst,
2460 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
2461 EVEX_V512, EVEX_CD8<32, CD8VF>;
2462 def PDZr_Int : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2463 !strconcat(OpcodeStr,
2464 "pd\t{$src, $dst|$dst, $src}"),
2465 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
2466 EVEX, EVEX_V512, VEX_W;
2467 def PDZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2468 !strconcat(OpcodeStr,
2469 "pd\t{$src, $dst|$dst, $src}"),
2470 [(set VR512:$dst,
2471 (V8F64Int (memopv8f64 addr:$src)))]>,
2472 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2473}
2474
2475/// avx512_fp_unop_s - AVX-512 unops in scalar form.
2476multiclass avx512_fp_unop_s<bits<8> opc, string OpcodeStr,
2477 Intrinsic F32Int, Intrinsic F64Int> {
2478 let hasSideEffects = 0 in {
2479 def SSZr : AVX5128I<opc, MRMSrcReg, (outs FR32X:$dst),
2480 (ins FR32X:$src1, FR32X:$src2),
2481 !strconcat(OpcodeStr,
2482 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2483 []>, EVEX_4V;
2484 let mayLoad = 1 in {
2485 def SSZm : AVX5128I<opc, MRMSrcMem, (outs FR32X:$dst),
2486 (ins FR32X:$src1, f32mem:$src2),
2487 !strconcat(OpcodeStr,
2488 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2489 []>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2490 def SSZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR128X:$dst),
2491 (ins VR128X:$src1, ssmem:$src2),
2492 !strconcat(OpcodeStr,
2493 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2494 [(set VR128X:$dst, (F32Int VR128X:$src1, sse_load_f32:$src2))]>,
2495 EVEX_4V, EVEX_CD8<32, CD8VT1>;
2496 }
2497 def SDZr : AVX5128I<opc, MRMSrcReg, (outs FR64X:$dst),
2498 (ins FR64X:$src1, FR64X:$src2),
2499 !strconcat(OpcodeStr,
2500 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2501 EVEX_4V, VEX_W;
2502 let mayLoad = 1 in {
2503 def SDZm : AVX5128I<opc, MRMSrcMem, (outs FR64X:$dst),
2504 (ins FR64X:$src1, f64mem:$src2),
2505 !strconcat(OpcodeStr,
2506 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2507 EVEX_4V, VEX_W, EVEX_CD8<32, CD8VT1>;
2508 def SDZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR128X:$dst),
2509 (ins VR128X:$src1, sdmem:$src2),
2510 !strconcat(OpcodeStr,
2511 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2512 [(set VR128X:$dst, (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
2513 EVEX_4V, VEX_W, EVEX_CD8<32, CD8VT1>;
2514 }
2515}
2516}
2517
2518defm VRCP14 : avx512_fp_unop_s<0x4D, "vrcp14", int_x86_avx512_rcp14_ss,
2519 int_x86_avx512_rcp14_sd>,
2520 avx512_fp_unop_p<0x4C, "vrcp14", X86frcp>,
2521 avx512_fp_unop_p_int<0x4C, "vrcp14",
2522 int_x86_avx512_rcp14_ps_512, int_x86_avx512_rcp14_pd_512>;
2523
2524defm VRSQRT14 : avx512_fp_unop_s<0x4F, "vrsqrt14", int_x86_avx512_rsqrt14_ss,
2525 int_x86_avx512_rsqrt14_sd>,
2526 avx512_fp_unop_p<0x4E, "vrsqrt14", X86frsqrt>,
2527 avx512_fp_unop_p_int<0x4E, "vrsqrt14",
2528 int_x86_avx512_rsqrt14_ps_512, int_x86_avx512_rsqrt14_pd_512>;
2529
2530multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
2531 Intrinsic V16F32Int, Intrinsic V8F64Int,
2532 OpndItins itins_s, OpndItins itins_d> {
2533 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2534 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2535 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
2536 EVEX, EVEX_V512;
2537
2538 let mayLoad = 1 in
2539 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2540 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2541 [(set VR512:$dst,
2542 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
2543 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2544
2545 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2546 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2547 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
2548 EVEX, EVEX_V512;
2549
2550 let mayLoad = 1 in
2551 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2552 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2553 [(set VR512:$dst, (OpNode
2554 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
2555 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
2556
2557 def PSZr_Int : AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2558 !strconcat(OpcodeStr,
2559 "ps\t{$src, $dst|$dst, $src}"),
2560 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
2561 EVEX, EVEX_V512;
2562 def PSZm_Int : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2563 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2564 [(set VR512:$dst,
2565 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
2566 EVEX_V512, EVEX_CD8<32, CD8VF>;
2567 def PDZr_Int : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2568 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2569 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
2570 EVEX, EVEX_V512, VEX_W;
2571 def PDZm_Int : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2572 !strconcat(OpcodeStr,
2573 "pd\t{$src, $dst|$dst, $src}"),
2574 [(set VR512:$dst, (V8F64Int (memopv8f64 addr:$src)))]>,
2575 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2576}
2577
2578multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
2579 Intrinsic F32Int, Intrinsic F64Int,
2580 OpndItins itins_s, OpndItins itins_d> {
2581 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
2582 (ins FR32X:$src1, FR32X:$src2),
2583 !strconcat(OpcodeStr,
2584 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2585 [], itins_s.rr>, XS, EVEX_4V;
2586 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
2587 (ins VR128X:$src1, VR128X:$src2),
2588 !strconcat(OpcodeStr,
2589 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2590 [(set VR128X:$dst,
2591 (F32Int VR128X:$src1, VR128X:$src2))],
2592 itins_s.rr>, XS, EVEX_4V;
2593 let mayLoad = 1 in {
2594 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
2595 (ins FR32X:$src1, f32mem:$src2),
2596 !strconcat(OpcodeStr,
2597 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2598 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2599 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
2600 (ins VR128X:$src1, ssmem:$src2),
2601 !strconcat(OpcodeStr,
2602 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2603 [(set VR128X:$dst,
2604 (F32Int VR128X:$src1, sse_load_f32:$src2))],
2605 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2606 }
2607 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
2608 (ins FR64X:$src1, FR64X:$src2),
2609 !strconcat(OpcodeStr,
2610 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2611 XD, EVEX_4V, VEX_W;
2612 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
2613 (ins VR128X:$src1, VR128X:$src2),
2614 !strconcat(OpcodeStr,
2615 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2616 [(set VR128X:$dst,
2617 (F64Int VR128X:$src1, VR128X:$src2))],
2618 itins_s.rr>, XD, EVEX_4V, VEX_W;
2619 let mayLoad = 1 in {
2620 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
2621 (ins FR64X:$src1, f64mem:$src2),
2622 !strconcat(OpcodeStr,
2623 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2624 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
2625 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
2626 (ins VR128X:$src1, sdmem:$src2),
2627 !strconcat(OpcodeStr,
2628 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2629 [(set VR128X:$dst,
2630 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
2631 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
2632 }
2633}
2634
2635
2636defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
2637 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
2638 SSE_SQRTSS, SSE_SQRTSD>,
2639 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
2640 int_x86_avx512_sqrt_ps_512, int_x86_avx512_sqrt_pd_512,
2641 SSE_SQRTPS, SSE_SQRTPD>;
2642
2643def : Pat<(f32 (fsqrt FR32X:$src)),
2644 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
2645def : Pat<(f32 (fsqrt (load addr:$src))),
2646 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
2647 Requires<[OptForSize]>;
2648def : Pat<(f64 (fsqrt FR64X:$src)),
2649 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
2650def : Pat<(f64 (fsqrt (load addr:$src))),
2651 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
2652 Requires<[OptForSize]>;
2653
2654def : Pat<(f32 (X86frsqrt FR32X:$src)),
2655 (VRSQRT14SSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
2656def : Pat<(f32 (X86frsqrt (load addr:$src))),
2657 (VRSQRT14SSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
2658 Requires<[OptForSize]>;
2659
2660def : Pat<(f32 (X86frcp FR32X:$src)),
2661 (VRCP14SSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
2662def : Pat<(f32 (X86frcp (load addr:$src))),
2663 (VRCP14SSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
2664 Requires<[OptForSize]>;
2665
2666multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
2667 X86MemOperand x86memop, RegisterClass RC,
2668 PatFrag mem_frag32, PatFrag mem_frag64,
2669 Intrinsic V4F32Int, Intrinsic V2F64Int,
2670 CD8VForm VForm> {
2671let ExeDomain = SSEPackedSingle in {
2672 // Intrinsic operation, reg.
2673 // Vector intrinsic operation, reg
2674 def PSr : AVX512AIi8<opcps, MRMSrcReg,
2675 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
2676 !strconcat(OpcodeStr,
2677 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2678 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
2679
2680 // Vector intrinsic operation, mem
2681 def PSm : AVX512AIi8<opcps, MRMSrcMem,
2682 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
2683 !strconcat(OpcodeStr,
2684 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2685 [(set RC:$dst,
2686 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
2687 EVEX_CD8<32, VForm>;
2688} // ExeDomain = SSEPackedSingle
2689
2690let ExeDomain = SSEPackedDouble in {
2691 // Vector intrinsic operation, reg
2692 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
2693 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
2694 !strconcat(OpcodeStr,
2695 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2696 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
2697
2698 // Vector intrinsic operation, mem
2699 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
2700 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
2701 !strconcat(OpcodeStr,
2702 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2703 [(set RC:$dst,
2704 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
2705 EVEX_CD8<64, VForm>;
2706} // ExeDomain = SSEPackedDouble
2707}
2708
2709multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
2710 string OpcodeStr,
2711 Intrinsic F32Int,
2712 Intrinsic F64Int> {
2713let ExeDomain = GenericDomain in {
2714 // Operation, reg.
2715 let hasSideEffects = 0 in
2716 def SSr : AVX512AIi8<opcss, MRMSrcReg,
2717 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
2718 !strconcat(OpcodeStr,
2719 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2720 []>;
2721
2722 // Intrinsic operation, reg.
2723 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
2724 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
2725 !strconcat(OpcodeStr,
2726 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2727 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
2728
2729 // Intrinsic operation, mem.
2730 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
2731 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
2732 !strconcat(OpcodeStr,
2733 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2734 [(set VR128X:$dst, (F32Int VR128X:$src1,
2735 sse_load_f32:$src2, imm:$src3))]>,
2736 EVEX_CD8<32, CD8VT1>;
2737
2738 // Operation, reg.
2739 let hasSideEffects = 0 in
2740 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
2741 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
2742 !strconcat(OpcodeStr,
2743 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2744 []>, VEX_W;
2745
2746 // Intrinsic operation, reg.
2747 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
2748 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
2749 !strconcat(OpcodeStr,
2750 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2751 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
2752 VEX_W;
2753
2754 // Intrinsic operation, mem.
2755 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
2756 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
2757 !strconcat(OpcodeStr,
2758 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2759 [(set VR128X:$dst,
2760 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
2761 VEX_W, EVEX_CD8<64, CD8VT1>;
2762} // ExeDomain = GenericDomain
2763}
2764
2765let Predicates = [HasAVX512] in {
2766 defm VRNDSCALE : avx512_fp_binop_rm<0x0A, 0x0B, "vrndscale",
2767 int_x86_avx512_rndscale_ss,
2768 int_x86_avx512_rndscale_sd>, EVEX_4V;
2769
2770 defm VRNDSCALEZ : avx512_fp_unop_rm<0x08, 0x09, "vrndscale", f256mem, VR512,
2771 memopv16f32, memopv8f64,
2772 int_x86_avx512_rndscale_ps_512,
2773 int_x86_avx512_rndscale_pd_512, CD8VF>,
2774 EVEX, EVEX_V512;
2775}
2776
2777def : Pat<(ffloor FR32X:$src),
2778 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
2779def : Pat<(f64 (ffloor FR64X:$src)),
2780 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
2781def : Pat<(f32 (fnearbyint FR32X:$src)),
2782 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
2783def : Pat<(f64 (fnearbyint FR64X:$src)),
2784 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
2785def : Pat<(f32 (fceil FR32X:$src)),
2786 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
2787def : Pat<(f64 (fceil FR64X:$src)),
2788 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
2789def : Pat<(f32 (frint FR32X:$src)),
2790 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
2791def : Pat<(f64 (frint FR64X:$src)),
2792 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
2793def : Pat<(f32 (ftrunc FR32X:$src)),
2794 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
2795def : Pat<(f64 (ftrunc FR64X:$src)),
2796 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
2797
2798def : Pat<(v16f32 (ffloor VR512:$src)),
2799 (VRNDSCALEZPSr VR512:$src, (i32 0x1))>;
2800def : Pat<(v16f32 (fnearbyint VR512:$src)),
2801 (VRNDSCALEZPSr VR512:$src, (i32 0xC))>;
2802def : Pat<(v16f32 (fceil VR512:$src)),
2803 (VRNDSCALEZPSr VR512:$src, (i32 0x2))>;
2804def : Pat<(v16f32 (frint VR512:$src)),
2805 (VRNDSCALEZPSr VR512:$src, (i32 0x4))>;
2806def : Pat<(v16f32 (ftrunc VR512:$src)),
2807 (VRNDSCALEZPSr VR512:$src, (i32 0x3))>;
2808
2809def : Pat<(v8f64 (ffloor VR512:$src)),
2810 (VRNDSCALEZPDr VR512:$src, (i32 0x1))>;
2811def : Pat<(v8f64 (fnearbyint VR512:$src)),
2812 (VRNDSCALEZPDr VR512:$src, (i32 0xC))>;
2813def : Pat<(v8f64 (fceil VR512:$src)),
2814 (VRNDSCALEZPDr VR512:$src, (i32 0x2))>;
2815def : Pat<(v8f64 (frint VR512:$src)),
2816 (VRNDSCALEZPDr VR512:$src, (i32 0x4))>;
2817def : Pat<(v8f64 (ftrunc VR512:$src)),
2818 (VRNDSCALEZPDr VR512:$src, (i32 0x3))>;
2819
2820//-------------------------------------------------
2821// Integer truncate and extend operations
2822//-------------------------------------------------
2823
2824multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
2825 RegisterClass dstRC, RegisterClass srcRC,
2826 RegisterClass KRC, X86MemOperand x86memop> {
2827 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
2828 (ins srcRC:$src),
2829 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
2830 []>, EVEX;
2831
2832 def krr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
2833 (ins KRC:$mask, srcRC:$src),
2834 !strconcat(OpcodeStr,
2835 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
2836 []>, EVEX, EVEX_KZ;
2837
2838 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
2839 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2840 []>, EVEX;
2841}
2842defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
2843 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
2844defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
2845 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
2846defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
2847 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
2848defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
2849 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
2850defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
2851 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
2852defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
2853 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
2854defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
2855 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
2856defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
2857 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
2858defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
2859 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
2860defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
2861 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
2862defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
2863 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
2864defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
2865 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
2866defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
2867 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
2868defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
2869 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
2870defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
2871 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
2872
2873def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
2874def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
2875def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
2876def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
2877def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
2878
2879def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
2880 (VPMOVDBkrr VK16WM:$mask, VR512:$src)>;
2881def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
2882 (VPMOVDWkrr VK16WM:$mask, VR512:$src)>;
2883def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
2884 (VPMOVQWkrr VK8WM:$mask, VR512:$src)>;
2885def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
2886 (VPMOVQDkrr VK8WM:$mask, VR512:$src)>;
2887
2888
2889multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass DstRC,
2890 RegisterClass SrcRC, SDNode OpNode, PatFrag mem_frag,
2891 X86MemOperand x86memop, ValueType OpVT, ValueType InVT> {
2892
2893 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
2894 (ins SrcRC:$src),
2895 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2896 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
2897 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
2898 (ins x86memop:$src),
2899 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
2900 [(set DstRC:$dst,
2901 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
2902 EVEX;
2903}
2904
2905defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VR512, VR128X, X86vzext,
2906 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
2907 EVEX_CD8<8, CD8VQ>;
2908defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VR512, VR128X, X86vzext,
2909 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
2910 EVEX_CD8<8, CD8VO>;
2911defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VR512, VR256X, X86vzext,
2912 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
2913 EVEX_CD8<16, CD8VH>;
2914defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VR512, VR128X, X86vzext,
2915 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
2916 EVEX_CD8<16, CD8VQ>;
2917defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VR512, VR256X, X86vzext,
2918 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
2919 EVEX_CD8<32, CD8VH>;
2920
2921defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VR512, VR128X, X86vsext,
2922 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
2923 EVEX_CD8<8, CD8VQ>;
2924defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VR512, VR128X, X86vsext,
2925 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
2926 EVEX_CD8<8, CD8VO>;
2927defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VR512, VR256X, X86vsext,
2928 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
2929 EVEX_CD8<16, CD8VH>;
2930defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VR512, VR128X, X86vsext,
2931 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
2932 EVEX_CD8<16, CD8VQ>;
2933defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VR512, VR256X, X86vsext,
2934 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
2935 EVEX_CD8<32, CD8VH>;
2936
2937//===----------------------------------------------------------------------===//
2938// GATHER - SCATTER Operations
2939
2940multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2941 RegisterClass RC, X86MemOperand memop> {
2942let mayLoad = 1,
2943 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
2944 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
2945 (ins RC:$src1, KRC:$mask, memop:$src2),
2946 !strconcat(OpcodeStr,
2947 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
2948 []>, EVEX, EVEX_K;
2949}
2950defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
2951 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
2952defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
2953 EVEX_V512, EVEX_CD8<32, CD8VT1>;
2954
2955defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
2956 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
2957defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
2958 EVEX_V512, EVEX_CD8<32, CD8VT1>;
2959
2960defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
2961 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
2962defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
2963 EVEX_V512, EVEX_CD8<32, CD8VT1>;
2964
2965defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
2966 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
2967defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
2968 EVEX_V512, EVEX_CD8<32, CD8VT1>;
2969
2970multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2971 RegisterClass RC, X86MemOperand memop> {
2972let mayStore = 1, Constraints = "$mask = $mask_wb" in
2973 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
2974 (ins memop:$dst, KRC:$mask, RC:$src2),
2975 !strconcat(OpcodeStr,
2976 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
2977 []>, EVEX, EVEX_K;
2978}
2979
2980defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
2981 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
2982defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
2983 EVEX_V512, EVEX_CD8<32, CD8VT1>;
2984
2985defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
2986 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
2987defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
2988 EVEX_V512, EVEX_CD8<32, CD8VT1>;
2989
2990defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
2991 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
2992defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
2993 EVEX_V512, EVEX_CD8<32, CD8VT1>;
2994
2995defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
2996 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
2997defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
2998 EVEX_V512, EVEX_CD8<32, CD8VT1>;
2999
3000//===----------------------------------------------------------------------===//
3001// VSHUFPS - VSHUFPD Operations
3002
3003multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
3004 ValueType vt, string OpcodeStr, PatFrag mem_frag,
3005 Domain d> {
3006 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
3007 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3008 !strconcat(OpcodeStr,
3009 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3010 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
3011 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
3012 EVEX_4V, TB, Sched<[WriteShuffleLd, ReadAfterLd]>;
3013 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
3014 (ins RC:$src1, RC:$src2, i8imm:$src3),
3015 !strconcat(OpcodeStr,
3016 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3017 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
3018 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
3019 EVEX_4V, TB, Sched<[WriteShuffle]>;
3020}
3021
3022defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
3023 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3024defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
3025 SSEPackedDouble>, OpSize, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3026
3027
3028multiclass avx512_alignr<string OpcodeStr, RegisterClass RC,
3029 X86MemOperand x86memop> {
3030 def rri : AVX512AIi8<0x03, MRMSrcReg, (outs RC:$dst),
3031 (ins RC:$src1, RC:$src2, i8imm:$src3),
3032 !strconcat(OpcodeStr,
3033 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3034 []>, EVEX_4V;
3035 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs RC:$dst),
3036 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3037 !strconcat(OpcodeStr,
3038 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3039 []>, EVEX_4V;
3040}
3041defm VALIGND : avx512_alignr<"valignd", VR512, i512mem>,
3042 EVEX_V512, EVEX_CD8<32, CD8VF>;
3043defm VALIGNQ : avx512_alignr<"valignq", VR512, i512mem>,
3044 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3045
3046def : Pat<(v16f32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3047 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3048def : Pat<(v8f64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3049 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3050def : Pat<(v16i32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3051 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3052def : Pat<(v8i64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3053 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3054
3055multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, RegisterClass RC,
3056 X86MemOperand x86memop> {
3057 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3058 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
3059 EVEX;
3060 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
3061 (ins x86memop:$src),
3062 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
3063 EVEX;
3064}
3065
3066defm VPABSD : avx512_vpabs<0x1E, "vpabsd", VR512, i512mem>, EVEX_V512,
3067 EVEX_CD8<32, CD8VF>;
3068defm VPABSQ : avx512_vpabs<0x1F, "vpabsq", VR512, i512mem>, EVEX_V512, VEX_W,
3069 EVEX_CD8<64, CD8VF>;
3070