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gerrit-public.fairphone.software / toolchain / llvm-project / 9004444d815579e01c393553f598ffbe9da4564b / . / llvm / test / CodeGen / PowerPC / atomics-indexed.ll
blob: b4790adfd90889906f51c6a149db5c069ffb66f2 [file] [log] [blame]
Kit Barton7c80f982018-08-28 01:18:29 +0000[diff] [blame]1; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -verify-machineinstrs -ppc-asm-full-reg-names | FileCheck %s --check-prefix=CHECK --check-prefix=PPC32
Robin Morissete1ca44b2014-10-02 22:27:07 +0000[diff] [blame]2; FIXME: -verify-machineinstrs currently fail on ppc64 (mismatched register/instruction).
3; This is already checked for in Atomics-64.ll
Kit Barton7c80f982018-08-28 01:18:29 +0000[diff] [blame]4; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -ppc-asm-full-reg-names | FileCheck %s --check-prefix=CHECK --check-prefix=PPC64
Robin Morissete1ca44b2014-10-02 22:27:07 +0000[diff] [blame]5
6; In this file, we check that atomic load/store can make use of the indexed
7; versions of the instructions.
8
9; Indexed version of loads
10define i8 @load_x_i8_seq_cst([100000 x i8]* %mem) {
11; CHECK-LABEL: load_x_i8_seq_cst
Hal Finkeld86e90a2015-04-23 23:05:08 +0000[diff] [blame]12; CHECK: sync
Tim Shen3bef27c2017-05-16 20:18:06 +0000[diff] [blame]13; CHECK: lbzx [[VAL:r[0-9]+]]
14; CHECK-PPC32: lwsync
15; CHECK-PPC64: cmpw [[CR:cr[0-9]+]], [[VAL]], [[VAL]]
16; CHECK-PPC64: bne- [[CR]], .+4
17; CHECK-PPC64: isync
David Blaikie79e6c742015-02-27 19:29:02 +0000[diff] [blame]18 %ptr = getelementptr inbounds [100000 x i8], [100000 x i8]* %mem, i64 0, i64 90000
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]19 %val = load atomic i8, i8* %ptr seq_cst, align 1
Robin Morissete1ca44b2014-10-02 22:27:07 +0000[diff] [blame]20 ret i8 %val
21}
22define i16 @load_x_i16_acquire([100000 x i16]* %mem) {
23; CHECK-LABEL: load_x_i16_acquire
Tim Shen3bef27c2017-05-16 20:18:06 +0000[diff] [blame]24; CHECK: lhzx [[VAL:r[0-9]+]]
25; CHECK-PPC32: lwsync
26; CHECK-PPC64: cmpw [[CR:cr[0-9]+]], [[VAL]], [[VAL]]
27; CHECK-PPC64: bne- [[CR]], .+4
28; CHECK-PPC64: isync
David Blaikie79e6c742015-02-27 19:29:02 +0000[diff] [blame]29 %ptr = getelementptr inbounds [100000 x i16], [100000 x i16]* %mem, i64 0, i64 90000
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]30 %val = load atomic i16, i16* %ptr acquire, align 2
Robin Morissete1ca44b2014-10-02 22:27:07 +0000[diff] [blame]31 ret i16 %val
32}
33define i32 @load_x_i32_monotonic([100000 x i32]* %mem) {
34; CHECK-LABEL: load_x_i32_monotonic
35; CHECK: lwzx
36; CHECK-NOT: sync
David Blaikie79e6c742015-02-27 19:29:02 +0000[diff] [blame]37 %ptr = getelementptr inbounds [100000 x i32], [100000 x i32]* %mem, i64 0, i64 90000
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]38 %val = load atomic i32, i32* %ptr monotonic, align 4
Robin Morissete1ca44b2014-10-02 22:27:07 +0000[diff] [blame]39 ret i32 %val
40}
41define i64 @load_x_i64_unordered([100000 x i64]* %mem) {
42; CHECK-LABEL: load_x_i64_unordered
43; PPC32: __sync_
44; PPC64-NOT: __sync_
45; PPC64: ldx
46; CHECK-NOT: sync
David Blaikie79e6c742015-02-27 19:29:02 +0000[diff] [blame]47 %ptr = getelementptr inbounds [100000 x i64], [100000 x i64]* %mem, i64 0, i64 90000
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]48 %val = load atomic i64, i64* %ptr unordered, align 8
Robin Morissete1ca44b2014-10-02 22:27:07 +0000[diff] [blame]49 ret i64 %val
50}
51
52; Indexed version of stores
53define void @store_x_i8_seq_cst([100000 x i8]* %mem) {
54; CHECK-LABEL: store_x_i8_seq_cst
Hal Finkeld86e90a2015-04-23 23:05:08 +0000[diff] [blame]55; CHECK: sync
Robin Morissete1ca44b2014-10-02 22:27:07 +0000[diff] [blame]56; CHECK: stbx
David Blaikie79e6c742015-02-27 19:29:02 +0000[diff] [blame]57 %ptr = getelementptr inbounds [100000 x i8], [100000 x i8]* %mem, i64 0, i64 90000
Robin Morissete1ca44b2014-10-02 22:27:07 +0000[diff] [blame]58 store atomic i8 42, i8* %ptr seq_cst, align 1
59 ret void
60}
61define void @store_x_i16_release([100000 x i16]* %mem) {
62; CHECK-LABEL: store_x_i16_release
Hal Finkel7c5cb062015-04-23 18:30:38 +0000[diff] [blame]63; CHECK: lwsync
Robin Morissete1ca44b2014-10-02 22:27:07 +0000[diff] [blame]64; CHECK: sthx
David Blaikie79e6c742015-02-27 19:29:02 +0000[diff] [blame]65 %ptr = getelementptr inbounds [100000 x i16], [100000 x i16]* %mem, i64 0, i64 90000
Robin Morissete1ca44b2014-10-02 22:27:07 +0000[diff] [blame]66 store atomic i16 42, i16* %ptr release, align 2
67 ret void
68}
69define void @store_x_i32_monotonic([100000 x i32]* %mem) {
70; CHECK-LABEL: store_x_i32_monotonic
71; CHECK-NOT: sync
72; CHECK: stwx
David Blaikie79e6c742015-02-27 19:29:02 +0000[diff] [blame]73 %ptr = getelementptr inbounds [100000 x i32], [100000 x i32]* %mem, i64 0, i64 90000
Robin Morissete1ca44b2014-10-02 22:27:07 +0000[diff] [blame]74 store atomic i32 42, i32* %ptr monotonic, align 4
75 ret void
76}
77define void @store_x_i64_unordered([100000 x i64]* %mem) {
78; CHECK-LABEL: store_x_i64_unordered
Hal Finkeld86e90a2015-04-23 23:05:08 +0000[diff] [blame]79; CHECK-NOT: sync
Robin Morissete1ca44b2014-10-02 22:27:07 +0000[diff] [blame]80; PPC32: __sync_
81; PPC64-NOT: __sync_
82; PPC64: stdx
David Blaikie79e6c742015-02-27 19:29:02 +0000[diff] [blame]83 %ptr = getelementptr inbounds [100000 x i64], [100000 x i64]* %mem, i64 0, i64 90000
Robin Morissete1ca44b2014-10-02 22:27:07 +0000[diff] [blame]84 store atomic i64 42, i64* %ptr unordered, align 8
85 ret void
86}