blob: be9df368df425a782d797b00daf71acdf6240cd6 [file] [log] [blame]
Zaara Syeda50ce30c2017-09-21 17:05:47 +00001; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -ppc-enable-gpr-to-vsr-spills < %s | FileCheck %s
Zaara Syedafcd96972017-09-21 16:12:33 +00002define signext i32 @foo(i32 signext %a, i32 signext %b) {
3entry:
4 %cmp = icmp slt i32 %a, %b
5 br i1 %cmp, label %if.then, label %if.end
6
7if.then: ; preds = %entry
8 %0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{r0},~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29}"(i32 %a, i32 %b)
9 %mul = mul nsw i32 %0, %a
10 %add = add i32 %b, %a
11 %tmp = add i32 %add, %mul
12 br label %if.end
13
14if.end: ; preds = %if.then, %entry
15 %e.0 = phi i32 [ %tmp, %if.then ], [ undef, %entry ]
16 ret i32 %e.0
17; CHECK: @foo
18; CHECK: mr [[NEWREG:[0-9]+]], 3
Geoff Berrya2b90112018-02-27 16:59:10 +000019; CHECK: mr [[REG1:[0-9]+]], 4
Zaara Syedafcd96972017-09-21 16:12:33 +000020; CHECK: mtvsrd [[NEWREG2:[0-9]+]], 4
Zaara Syedafcd96972017-09-21 16:12:33 +000021; CHECK: add {{[0-9]+}}, [[NEWREG]], [[REG1]]
22; CHECK: mffprd [[REG2:[0-9]+]], [[NEWREG2]]
23; CHECK: add {{[0-9]+}}, [[REG2]], [[NEWREG]]
24}