blob: 70627151cc6329b6dfbd2ff9834dae6067df9ff1 [file] [log] [blame]
Valery Pykhtincb8de552019-06-07 12:16:46 +00001; RUN: opt -mtriple=amdgcn-- --amdgpu-inline -S -amdgpu-inline-max-bb=2 %s | FileCheck %s --check-prefix=NOINL
2; RUN: opt -mtriple=amdgcn-- --amdgpu-inline -S -amdgpu-inline-max-bb=3 %s | FileCheck %s --check-prefix=INL
3
4define i32 @callee(i32 %x) {
5entry:
6 %cc = icmp eq i32 %x, 1
7 br i1 %cc, label %ret_res, label %mulx
8
9mulx:
10 %mul1 = mul i32 %x, %x
11 %mul2 = mul i32 %mul1, %x
12 %mul3 = mul i32 %mul1, %mul2
13 %mul4 = mul i32 %mul3, %mul2
14 %mul5 = mul i32 %mul4, %mul3
15 br label %ret_res
16
17ret_res:
18 %r = phi i32 [ %mul5, %mulx ], [ %x, %entry ]
19 ret i32 %r
20}
21
22; INL-LABEL: @caller
23; NOINL-LABEL: @caller
24; INL: mul i32
25; INL-NOT: call i32
26; NOINL-NOT: mul i32
27; NOINL: call i32
28
29define amdgpu_kernel void @caller(i32 %x) {
30 %res = call i32 @callee(i32 %x)
31 store volatile i32 %res, i32 addrspace(1)* undef
32 ret void
33}
Valery Pykhtinffeb01c2019-06-14 16:37:33 +000034
35
36; inlinehint
37define i32 @callee_hint(i32 %x) #0 {
38entry:
39 %cc = icmp eq i32 %x, 1
40 br i1 %cc, label %ret_res, label %mulx
41
42mulx:
43 %mul1 = mul i32 %x, %x
44 %mul2 = mul i32 %mul1, %x
45 %mul3 = mul i32 %mul1, %mul2
46 %mul4 = mul i32 %mul3, %mul2
47 %mul5 = mul i32 %mul4, %mul3
48 br label %ret_res
49
50ret_res:
51 %r = phi i32 [ %mul5, %mulx ], [ %x, %entry ]
52 ret i32 %r
53}
54
55; INL-LABEL: @caller_hint
56; NOINL-LABEL: @caller_hint
57; INL: mul i32
58; INL-NOT: call i32
59; NOINL: mul i32
60; NOINL-NOT: call i32
61
62define amdgpu_kernel void @caller_hint(i32 %x) {
63 %res = call i32 @callee_hint(i32 %x)
64 store volatile i32 %res, i32 addrspace(1)* undef
65 ret void
66}
67
68attributes #0 = { inlinehint }