Matt Arsenault | 8c8fcb2 | 2016-03-25 01:16:40 +0000 | [diff] [blame] | 1 | ; RUN: opt -cost-model -analyze -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck %s |
| 2 | |
| 3 | ; CHECK: 'or_i32' |
| 4 | ; CHECK: estimated cost of 1 for {{.*}} or i32 |
Matt Arsenault | 3dbeefa | 2017-03-21 21:39:51 +0000 | [diff] [blame] | 5 | define amdgpu_kernel void @or_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %vaddr, i32 %b) #0 { |
Matt Arsenault | 8c8fcb2 | 2016-03-25 01:16:40 +0000 | [diff] [blame] | 6 | %vec = load i32, i32 addrspace(1)* %vaddr |
| 7 | %or = or i32 %vec, %b |
| 8 | store i32 %or, i32 addrspace(1)* %out |
| 9 | ret void |
| 10 | } |
| 11 | |
| 12 | ; CHECK: 'or_i64' |
| 13 | ; CHECK: estimated cost of 2 for {{.*}} or i64 |
Matt Arsenault | 3dbeefa | 2017-03-21 21:39:51 +0000 | [diff] [blame] | 14 | define amdgpu_kernel void @or_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %vaddr, i64 %b) #0 { |
Matt Arsenault | 8c8fcb2 | 2016-03-25 01:16:40 +0000 | [diff] [blame] | 15 | %vec = load i64, i64 addrspace(1)* %vaddr |
| 16 | %or = or i64 %vec, %b |
| 17 | store i64 %or, i64 addrspace(1)* %out |
| 18 | ret void |
| 19 | } |
| 20 | |
| 21 | ; CHECK: 'xor_i32' |
| 22 | ; CHECK: estimated cost of 1 for {{.*}} xor i32 |
Matt Arsenault | 3dbeefa | 2017-03-21 21:39:51 +0000 | [diff] [blame] | 23 | define amdgpu_kernel void @xor_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %vaddr, i32 %b) #0 { |
Matt Arsenault | 8c8fcb2 | 2016-03-25 01:16:40 +0000 | [diff] [blame] | 24 | %vec = load i32, i32 addrspace(1)* %vaddr |
| 25 | %or = xor i32 %vec, %b |
| 26 | store i32 %or, i32 addrspace(1)* %out |
| 27 | ret void |
| 28 | } |
| 29 | |
| 30 | ; CHECK: 'xor_i64' |
| 31 | ; CHECK: estimated cost of 2 for {{.*}} xor i64 |
Matt Arsenault | 3dbeefa | 2017-03-21 21:39:51 +0000 | [diff] [blame] | 32 | define amdgpu_kernel void @xor_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %vaddr, i64 %b) #0 { |
Matt Arsenault | 8c8fcb2 | 2016-03-25 01:16:40 +0000 | [diff] [blame] | 33 | %vec = load i64, i64 addrspace(1)* %vaddr |
| 34 | %or = xor i64 %vec, %b |
| 35 | store i64 %or, i64 addrspace(1)* %out |
| 36 | ret void |
| 37 | } |
| 38 | |
| 39 | |
| 40 | ; CHECK: 'and_i32' |
| 41 | ; CHECK: estimated cost of 1 for {{.*}} and i32 |
Matt Arsenault | 3dbeefa | 2017-03-21 21:39:51 +0000 | [diff] [blame] | 42 | define amdgpu_kernel void @and_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %vaddr, i32 %b) #0 { |
Matt Arsenault | 8c8fcb2 | 2016-03-25 01:16:40 +0000 | [diff] [blame] | 43 | %vec = load i32, i32 addrspace(1)* %vaddr |
| 44 | %or = and i32 %vec, %b |
| 45 | store i32 %or, i32 addrspace(1)* %out |
| 46 | ret void |
| 47 | } |
| 48 | |
| 49 | ; CHECK: 'and_i64' |
| 50 | ; CHECK: estimated cost of 2 for {{.*}} and i64 |
Matt Arsenault | 3dbeefa | 2017-03-21 21:39:51 +0000 | [diff] [blame] | 51 | define amdgpu_kernel void @and_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %vaddr, i64 %b) #0 { |
Matt Arsenault | 8c8fcb2 | 2016-03-25 01:16:40 +0000 | [diff] [blame] | 52 | %vec = load i64, i64 addrspace(1)* %vaddr |
| 53 | %or = and i64 %vec, %b |
| 54 | store i64 %or, i64 addrspace(1)* %out |
| 55 | ret void |
| 56 | } |
| 57 | |
| 58 | |
| 59 | attributes #0 = { nounwind } |