blob: 0cd2d7ed84a73122675d1ed0899a6e66ed7f4e92 [file] [log] [blame]
Tim Northover20603722014-04-15 13:59:40 +00001; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64 | FileCheck %s
Tim Northovere0e3aef2013-01-31 12:12:40 +00002
3@var32_0 = global i32 0
4@var32_1 = global i32 0
5@var64_0 = global i64 0
6@var64_1 = global i64 0
7
8define void @rorv_i64() {
Stephen Lind24ab202013-07-14 06:24:09 +00009; CHECK-LABEL: rorv_i64:
David Blaikiea79ac142015-02-27 21:17:42 +000010 %val0_tmp = load i64, i64* @var64_0
11 %val1_tmp = load i64, i64* @var64_1
Tim Northovere0e3aef2013-01-31 12:12:40 +000012 %val2_tmp = sub i64 64, %val1_tmp
13 %val3_tmp = shl i64 %val0_tmp, %val2_tmp
14 %val4_tmp = lshr i64 %val0_tmp, %val1_tmp
15 %val5_tmp = or i64 %val3_tmp, %val4_tmp
Tim Northover20603722014-04-15 13:59:40 +000016; CHECK: {{ror|rorv}} {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
Tim Northovere0e3aef2013-01-31 12:12:40 +000017 store volatile i64 %val5_tmp, i64* @var64_0
18 ret void
19}
20
21define void @asrv_i64() {
Stephen Lind24ab202013-07-14 06:24:09 +000022; CHECK-LABEL: asrv_i64:
David Blaikiea79ac142015-02-27 21:17:42 +000023 %val0_tmp = load i64, i64* @var64_0
24 %val1_tmp = load i64, i64* @var64_1
Tim Northovere0e3aef2013-01-31 12:12:40 +000025 %val4_tmp = ashr i64 %val0_tmp, %val1_tmp
Tim Northover20603722014-04-15 13:59:40 +000026; CHECK: {{asr|asrv}} {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
Tim Northovere0e3aef2013-01-31 12:12:40 +000027 store volatile i64 %val4_tmp, i64* @var64_1
28 ret void
29}
30
31define void @lsrv_i64() {
Stephen Lind24ab202013-07-14 06:24:09 +000032; CHECK-LABEL: lsrv_i64:
David Blaikiea79ac142015-02-27 21:17:42 +000033 %val0_tmp = load i64, i64* @var64_0
34 %val1_tmp = load i64, i64* @var64_1
Tim Northovere0e3aef2013-01-31 12:12:40 +000035 %val4_tmp = lshr i64 %val0_tmp, %val1_tmp
Tim Northover20603722014-04-15 13:59:40 +000036; CHECK: {{lsr|lsrv}} {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
Tim Northovere0e3aef2013-01-31 12:12:40 +000037 store volatile i64 %val4_tmp, i64* @var64_0
38 ret void
39}
40
41define void @lslv_i64() {
Stephen Lind24ab202013-07-14 06:24:09 +000042; CHECK-LABEL: lslv_i64:
David Blaikiea79ac142015-02-27 21:17:42 +000043 %val0_tmp = load i64, i64* @var64_0
44 %val1_tmp = load i64, i64* @var64_1
Tim Northovere0e3aef2013-01-31 12:12:40 +000045 %val4_tmp = shl i64 %val0_tmp, %val1_tmp
Tim Northover20603722014-04-15 13:59:40 +000046; CHECK: {{lsl|lslv}} {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
Tim Northovere0e3aef2013-01-31 12:12:40 +000047 store volatile i64 %val4_tmp, i64* @var64_1
48 ret void
49}
50
51define void @udiv_i64() {
Stephen Lind24ab202013-07-14 06:24:09 +000052; CHECK-LABEL: udiv_i64:
David Blaikiea79ac142015-02-27 21:17:42 +000053 %val0_tmp = load i64, i64* @var64_0
54 %val1_tmp = load i64, i64* @var64_1
Tim Northovere0e3aef2013-01-31 12:12:40 +000055 %val4_tmp = udiv i64 %val0_tmp, %val1_tmp
56; CHECK: udiv {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
57 store volatile i64 %val4_tmp, i64* @var64_0
58 ret void
59}
60
61define void @sdiv_i64() {
Stephen Lind24ab202013-07-14 06:24:09 +000062; CHECK-LABEL: sdiv_i64:
David Blaikiea79ac142015-02-27 21:17:42 +000063 %val0_tmp = load i64, i64* @var64_0
64 %val1_tmp = load i64, i64* @var64_1
Tim Northovere0e3aef2013-01-31 12:12:40 +000065 %val4_tmp = sdiv i64 %val0_tmp, %val1_tmp
66; CHECK: sdiv {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
67 store volatile i64 %val4_tmp, i64* @var64_1
68 ret void
69}
70
71
72define void @lsrv_i32() {
Stephen Lind24ab202013-07-14 06:24:09 +000073; CHECK-LABEL: lsrv_i32:
David Blaikiea79ac142015-02-27 21:17:42 +000074 %val0_tmp = load i32, i32* @var32_0
75 %val1_tmp = load i32, i32* @var32_1
Tim Northovere0e3aef2013-01-31 12:12:40 +000076 %val2_tmp = add i32 1, %val1_tmp
77 %val4_tmp = lshr i32 %val0_tmp, %val2_tmp
Tim Northover20603722014-04-15 13:59:40 +000078; CHECK: {{lsr|lsrv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
Tim Northovere0e3aef2013-01-31 12:12:40 +000079 store volatile i32 %val4_tmp, i32* @var32_0
80 ret void
81}
82
83define void @lslv_i32() {
Stephen Lind24ab202013-07-14 06:24:09 +000084; CHECK-LABEL: lslv_i32:
David Blaikiea79ac142015-02-27 21:17:42 +000085 %val0_tmp = load i32, i32* @var32_0
86 %val1_tmp = load i32, i32* @var32_1
Tim Northovere0e3aef2013-01-31 12:12:40 +000087 %val2_tmp = add i32 1, %val1_tmp
88 %val4_tmp = shl i32 %val0_tmp, %val2_tmp
Tim Northover20603722014-04-15 13:59:40 +000089; CHECK: {{lsl|lslv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
Tim Northovere0e3aef2013-01-31 12:12:40 +000090 store volatile i32 %val4_tmp, i32* @var32_1
91 ret void
92}
93
94define void @rorv_i32() {
Stephen Lind24ab202013-07-14 06:24:09 +000095; CHECK-LABEL: rorv_i32:
David Blaikiea79ac142015-02-27 21:17:42 +000096 %val0_tmp = load i32, i32* @var32_0
97 %val6_tmp = load i32, i32* @var32_1
Tim Northovere0e3aef2013-01-31 12:12:40 +000098 %val1_tmp = add i32 1, %val6_tmp
99 %val2_tmp = sub i32 32, %val1_tmp
100 %val3_tmp = shl i32 %val0_tmp, %val2_tmp
101 %val4_tmp = lshr i32 %val0_tmp, %val1_tmp
102 %val5_tmp = or i32 %val3_tmp, %val4_tmp
Tim Northover20603722014-04-15 13:59:40 +0000103; CHECK: {{ror|rorv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
Tim Northovere0e3aef2013-01-31 12:12:40 +0000104 store volatile i32 %val5_tmp, i32* @var32_0
105 ret void
106}
107
108define void @asrv_i32() {
Stephen Lind24ab202013-07-14 06:24:09 +0000109; CHECK-LABEL: asrv_i32:
David Blaikiea79ac142015-02-27 21:17:42 +0000110 %val0_tmp = load i32, i32* @var32_0
111 %val1_tmp = load i32, i32* @var32_1
Tim Northovere0e3aef2013-01-31 12:12:40 +0000112 %val2_tmp = add i32 1, %val1_tmp
113 %val4_tmp = ashr i32 %val0_tmp, %val2_tmp
Tim Northover20603722014-04-15 13:59:40 +0000114; CHECK: {{asr|asrv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
Tim Northovere0e3aef2013-01-31 12:12:40 +0000115 store volatile i32 %val4_tmp, i32* @var32_1
116 ret void
117}
118
119define void @sdiv_i32() {
Stephen Lind24ab202013-07-14 06:24:09 +0000120; CHECK-LABEL: sdiv_i32:
David Blaikiea79ac142015-02-27 21:17:42 +0000121 %val0_tmp = load i32, i32* @var32_0
122 %val1_tmp = load i32, i32* @var32_1
Tim Northovere0e3aef2013-01-31 12:12:40 +0000123 %val4_tmp = sdiv i32 %val0_tmp, %val1_tmp
124; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
125 store volatile i32 %val4_tmp, i32* @var32_1
126 ret void
127}
128
129define void @udiv_i32() {
Stephen Lind24ab202013-07-14 06:24:09 +0000130; CHECK-LABEL: udiv_i32:
David Blaikiea79ac142015-02-27 21:17:42 +0000131 %val0_tmp = load i32, i32* @var32_0
132 %val1_tmp = load i32, i32* @var32_1
Tim Northovere0e3aef2013-01-31 12:12:40 +0000133 %val4_tmp = udiv i32 %val0_tmp, %val1_tmp
134; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
135 store volatile i32 %val4_tmp, i32* @var32_0
136 ret void
137}
138
139; The point of this test is that we may not actually see (shl GPR32:$Val, (zext GPR32:$Val2))
140; in the DAG (the RHS may be natively 64-bit), but we should still use the lsl instructions.
141define i32 @test_lsl32() {
Stephen Linf799e3f2013-07-13 20:38:47 +0000142; CHECK-LABEL: test_lsl32:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000143
David Blaikiea79ac142015-02-27 21:17:42 +0000144 %val = load i32, i32* @var32_0
Tim Northovere0e3aef2013-01-31 12:12:40 +0000145 %ret = shl i32 1, %val
Tim Northover20603722014-04-15 13:59:40 +0000146; CHECK: {{lsl|lslv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
Tim Northovere0e3aef2013-01-31 12:12:40 +0000147
148 ret i32 %ret
149}
150
151define i32 @test_lsr32() {
Stephen Linf799e3f2013-07-13 20:38:47 +0000152; CHECK-LABEL: test_lsr32:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000153
David Blaikiea79ac142015-02-27 21:17:42 +0000154 %val = load i32, i32* @var32_0
Tim Northovere0e3aef2013-01-31 12:12:40 +0000155 %ret = lshr i32 1, %val
Tim Northover20603722014-04-15 13:59:40 +0000156; CHECK: {{lsr|lsrv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
Tim Northovere0e3aef2013-01-31 12:12:40 +0000157
158 ret i32 %ret
159}
160
161define i32 @test_asr32(i32 %in) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000162; CHECK-LABEL: test_asr32:
Tim Northovere0e3aef2013-01-31 12:12:40 +0000163
David Blaikiea79ac142015-02-27 21:17:42 +0000164 %val = load i32, i32* @var32_0
Tim Northovere0e3aef2013-01-31 12:12:40 +0000165 %ret = ashr i32 %in, %val
Tim Northover20603722014-04-15 13:59:40 +0000166; CHECK: {{asr|asrv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
Tim Northovere0e3aef2013-01-31 12:12:40 +0000167
168 ret i32 %ret
169}