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Krzysztof Parzyszek046090d2018-03-12 14:01:28 +00001; RUN: llc -march=hexagon < %s | FileCheck %s
2
3; Test that we generate a hardware loop for long long counters.
4; Tests signed/unsigned GT, EQ, and NEQ cases.
5
6; signed GT case
7; CHECK-LABEL: f0:
8; CHECK: loop0
9define i32 @f0(i32* nocapture %a0) #0 {
10b0:
11 br label %b1
12b1: ; preds = %b1, %b0
13 %v0 = phi i32 [ 0, %b0 ], [ %v5, %b1 ]
14 %v1 = phi i64 [ 0, %b0 ], [ %v6, %b1 ]
15 %v2 = trunc i64 %v1 to i32
16 %v3 = getelementptr inbounds i32, i32* %a0, i32 %v2
17 %v4 = load i32, i32* %v3, align 4
18 %v5 = add nsw i32 %v4, %v0
19 %v6 = add nsw i64 %v1, 1
20 %v7 = icmp slt i64 %v6, 8
21 br i1 %v7, label %b1, label %b2
22
23b2: ; preds = %b1
24 ret i32 %v5
25}
26
27; unsigned signed GT case
28; CHECK-LABEL: f1:
29; CHECK: loop0
30define i32 @f1(i32* nocapture %a0) #0 {
31b0:
32 br label %b1
33b1: ; preds = %b1, %b0
34 %v0 = phi i32 [ 0, %b0 ], [ %v5, %b1 ]
35 %v1 = phi i64 [ 0, %b0 ], [ %v6, %b1 ]
36 %v2 = trunc i64 %v1 to i32
37 %v3 = getelementptr inbounds i32, i32* %a0, i32 %v2
38 %v4 = load i32, i32* %v3, align 4
39 %v5 = add nsw i32 %v4, %v0
40 %v6 = add i64 %v1, 1
41 %v7 = icmp ult i64 %v6, 8
42 br i1 %v7, label %b1, label %b2
43
44b2: ; preds = %b1
45 ret i32 %v5
46}
47
48; EQ case
49; CHECK-LABEL: f2:
50; CHECK: loop0
51define i32 @f2(i32* nocapture %a0) #0 {
52b0:
53 br label %b1
54
55b1: ; preds = %b1, %b0
56 %v0 = phi i32 [ 0, %b0 ], [ %v5, %b1 ]
57 %v1 = phi i64 [ 0, %b0 ], [ %v6, %b1 ]
58 %v2 = trunc i64 %v1 to i32
59 %v3 = getelementptr inbounds i32, i32* %a0, i32 %v2
60 %v4 = load i32, i32* %v3, align 4
61 %v5 = add nsw i32 %v4, %v0
62 %v6 = add nsw i64 %v1, 1
63 %v7 = icmp eq i64 %v6, 8
64 br i1 %v7, label %b2, label %b1
65
66b2: ; preds = %b1
67 ret i32 %v5
68}
69
70attributes #0 = { nounwind readonly "target-cpu"="hexagonv55" }