Simon Atanasyan | 7572704 | 2018-10-03 22:02:23 +0000 | [diff] [blame] | 1 | ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 \ |
| 2 | ; RUN: | FileCheck %s -check-prefix=MIPS32 |
| 3 | ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -mattr=+micromips \ |
| 4 | ; RUN: | FileCheck %s -check-prefix=MM |
| 5 | ; RUN: llc < %s -march=mips64el -mcpu=mips64r2 \ |
| 6 | ; RUN: | FileCheck %s -check-prefix=MIPS64 |
| 7 | ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -mattr=+mips16 \ |
| 8 | ; RUN: | FileCheck %s -check-prefix=MIPS16 |
Akira Hatanaka | bd95275 | 2011-12-20 23:58:36 +0000 | [diff] [blame] | 9 | |
Daniel Sanders | c43cda8 | 2014-11-07 16:54:21 +0000 | [diff] [blame] | 10 | define i32 @bswap32(i32 signext %x) nounwind readnone { |
Akira Hatanaka | bd95275 | 2011-12-20 23:58:36 +0000 | [diff] [blame] | 11 | entry: |
Stephen Lin | d24ab20 | 2013-07-14 06:24:09 +0000 | [diff] [blame] | 12 | ; MIPS32-LABEL: bswap32: |
Akira Hatanaka | bd95275 | 2011-12-20 23:58:36 +0000 | [diff] [blame] | 13 | ; MIPS32: wsbh $[[R0:[0-9]+]] |
| 14 | ; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16 |
Daniel Sanders | daf7c02 | 2014-03-31 11:00:04 +0000 | [diff] [blame] | 15 | |
Simon Dardis | fce722e | 2018-04-24 10:19:29 +0000 | [diff] [blame] | 16 | ; MM-LABEL: bswap32: |
| 17 | ; MM: wsbh $[[R0:[0-9]+]] |
| 18 | ; MM: rotr ${{[0-9]+}}, $[[R0]], 16 |
| 19 | |
Daniel Sanders | daf7c02 | 2014-03-31 11:00:04 +0000 | [diff] [blame] | 20 | ; MIPS64-LABEL: bswap32: |
| 21 | ; MIPS64: wsbh $[[R0:[0-9]+]] |
| 22 | ; MIPS64: rotr ${{[0-9]+}}, $[[R0]], 16 |
| 23 | |
| 24 | ; MIPS16-LABEL: bswap32: |
| 25 | ; MIPS16-DAG: srl $[[R0:[0-9]+]], $4, 8 |
| 26 | ; MIPS16-DAG: srl $[[R1:[0-9]+]], $4, 24 |
| 27 | ; MIPS16-DAG: sll $[[R2:[0-9]+]], $4, 8 |
| 28 | ; MIPS16-DAG: sll $[[R3:[0-9]+]], $4, 24 |
| 29 | ; MIPS16-DAG: li $[[R4:[0-9]+]], 65280 |
| 30 | ; MIPS16-DAG: and $[[R4]], $[[R0]] |
| 31 | ; MIPS16-DAG: or $[[R1]], $[[R4]] |
| 32 | ; MIPS16-DAG: lw $[[R7:[0-9]+]], $CPI |
| 33 | ; MIPS16-DAG: and $[[R7]], $[[R2]] |
| 34 | ; MIPS16-DAG: or $[[R3]], $[[R7]] |
| 35 | ; MIPS16-DAG: or $[[R3]], $[[R1]] |
| 36 | |
Akira Hatanaka | bd95275 | 2011-12-20 23:58:36 +0000 | [diff] [blame] | 37 | %or.3 = call i32 @llvm.bswap.i32(i32 %x) |
| 38 | ret i32 %or.3 |
| 39 | } |
| 40 | |
Daniel Sanders | c43cda8 | 2014-11-07 16:54:21 +0000 | [diff] [blame] | 41 | define i64 @bswap64(i64 signext %x) nounwind readnone { |
Akira Hatanaka | bd95275 | 2011-12-20 23:58:36 +0000 | [diff] [blame] | 42 | entry: |
Daniel Sanders | daf7c02 | 2014-03-31 11:00:04 +0000 | [diff] [blame] | 43 | ; MIPS32-LABEL: bswap64: |
| 44 | ; MIPS32: wsbh $[[R0:[0-9]+]] |
| 45 | ; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16 |
| 46 | ; MIPS32: wsbh $[[R0:[0-9]+]] |
| 47 | ; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16 |
| 48 | |
Simon Dardis | fce722e | 2018-04-24 10:19:29 +0000 | [diff] [blame] | 49 | ; MM-LABEL: bswap64: |
| 50 | ; MM: wsbh $[[R0:[0-9]+]] |
| 51 | ; MM: rotr ${{[0-9]+}}, $[[R0]], 16 |
| 52 | ; MM: wsbh $[[R0:[0-9]+]] |
| 53 | ; MM: rotr ${{[0-9]+}}, $[[R0]], 16 |
| 54 | |
Stephen Lin | d24ab20 | 2013-07-14 06:24:09 +0000 | [diff] [blame] | 55 | ; MIPS64-LABEL: bswap64: |
Akira Hatanaka | bd95275 | 2011-12-20 23:58:36 +0000 | [diff] [blame] | 56 | ; MIPS64: dsbh $[[R0:[0-9]+]] |
| 57 | ; MIPS64: dshd ${{[0-9]+}}, $[[R0]] |
Daniel Sanders | daf7c02 | 2014-03-31 11:00:04 +0000 | [diff] [blame] | 58 | |
| 59 | ; MIPS16-LABEL: bswap64: |
| 60 | ; MIPS16-DAG: srl $[[R0:[0-9]+]], $5, 8 |
| 61 | ; MIPS16-DAG: srl $[[R1:[0-9]+]], $5, 24 |
| 62 | ; MIPS16-DAG: sll $[[R2:[0-9]+]], $5, 8 |
| 63 | ; MIPS16-DAG: sll $[[R3:[0-9]+]], $5, 24 |
| 64 | ; MIPS16-DAG: li $[[R4:[0-9]+]], 65280 |
| 65 | ; MIPS16-DAG: and $[[R0]], $[[R4]] |
| 66 | ; MIPS16-DAG: or $[[R1]], $[[R0]] |
| 67 | ; MIPS16-DAG: lw $[[R7:[0-9]+]], 1f |
| 68 | ; MIPS16-DAG: and $[[R2]], $[[R7]] |
| 69 | ; MIPS16-DAG: or $[[R3]], $[[R2]] |
| 70 | ; MIPS16-DAG: or $[[R3]], $[[R1]] |
| 71 | ; MIPS16-DAG: srl $[[R0:[0-9]+]], $4, 8 |
| 72 | ; MIPS16-DAG: srl $[[R1:[0-9]+]], $4, 24 |
| 73 | ; MIPS16-DAG: sll $[[R2:[0-9]+]], $4, 8 |
| 74 | ; MIPS16-DAG: sll $[[R3:[0-9]+]], $4, 24 |
Daniel Sanders | daf7c02 | 2014-03-31 11:00:04 +0000 | [diff] [blame] | 75 | ; MIPS16-DAG: and $[[R0]], $[[R4]] |
| 76 | ; MIPS16-DAG: or $[[R1]], $[[R0]] |
Daniel Sanders | daf7c02 | 2014-03-31 11:00:04 +0000 | [diff] [blame] | 77 | ; MIPS16-DAG: and $[[R2]], $[[R7]] |
| 78 | ; MIPS16-DAG: or $[[R3]], $[[R2]] |
| 79 | ; MIPS16-DAG: or $[[R3]], $[[R1]] |
| 80 | |
Akira Hatanaka | bd95275 | 2011-12-20 23:58:36 +0000 | [diff] [blame] | 81 | %or.7 = call i64 @llvm.bswap.i64(i64 %x) |
| 82 | ret i64 %or.7 |
| 83 | } |
| 84 | |
Raul E. Silvera | a9dafe6 | 2014-03-18 17:49:12 +0000 | [diff] [blame] | 85 | define <4 x i32> @bswapv4i32(<4 x i32> %x) nounwind readnone { |
| 86 | entry: |
| 87 | ; MIPS32-LABEL: bswapv4i32: |
Daniel Sanders | c43cda8 | 2014-11-07 16:54:21 +0000 | [diff] [blame] | 88 | ; MIPS32-DAG: wsbh $[[R0:[0-9]+]] |
| 89 | ; MIPS32-DAG: rotr ${{[0-9]+}}, $[[R0]], 16 |
| 90 | ; MIPS32-DAG: wsbh $[[R0:[0-9]+]] |
| 91 | ; MIPS32-DAG: rotr ${{[0-9]+}}, $[[R0]], 16 |
| 92 | ; MIPS32-DAG: wsbh $[[R0:[0-9]+]] |
| 93 | ; MIPS32-DAG: rotr ${{[0-9]+}}, $[[R0]], 16 |
| 94 | ; MIPS32-DAG: wsbh $[[R0:[0-9]+]] |
| 95 | ; MIPS32-DAG: rotr ${{[0-9]+}}, $[[R0]], 16 |
Daniel Sanders | daf7c02 | 2014-03-31 11:00:04 +0000 | [diff] [blame] | 96 | |
Simon Dardis | fce722e | 2018-04-24 10:19:29 +0000 | [diff] [blame] | 97 | ; MM-LABEL: bswapv4i32: |
| 98 | ; MM-DAG: wsbh $[[R0:[0-9]+]] |
| 99 | ; MM-DAG: rotr ${{[0-9]+}}, $[[R0]], 16 |
| 100 | ; MM-DAG: wsbh $[[R0:[0-9]+]] |
| 101 | ; MM-DAG: rotr ${{[0-9]+}}, $[[R0]], 16 |
| 102 | ; MM-DAG: wsbh $[[R0:[0-9]+]] |
| 103 | ; MM-DAG: rotr ${{[0-9]+}}, $[[R0]], 16 |
| 104 | ; MM-DAG: wsbh $[[R0:[0-9]+]] |
| 105 | ; MM-DAG: rotr ${{[0-9]+}}, $[[R0]], 16 |
| 106 | |
Daniel Sanders | daf7c02 | 2014-03-31 11:00:04 +0000 | [diff] [blame] | 107 | ; MIPS64-LABEL: bswapv4i32: |
Daniel Sanders | c43cda8 | 2014-11-07 16:54:21 +0000 | [diff] [blame] | 108 | ; MIPS64-DAG: wsbh $[[R0:[0-9]+]] |
| 109 | ; MIPS64-DAG: rotr ${{[0-9]+}}, $[[R0]], 16 |
| 110 | ; MIPS64-DAG: wsbh $[[R0:[0-9]+]] |
| 111 | ; MIPS64-DAG: rotr ${{[0-9]+}}, $[[R0]], 16 |
| 112 | ; MIPS64-DAG: wsbh $[[R0:[0-9]+]] |
| 113 | ; MIPS64-DAG: rotr ${{[0-9]+}}, $[[R0]], 16 |
| 114 | ; MIPS64-DAG: wsbh $[[R0:[0-9]+]] |
| 115 | ; MIPS64-DAG: rotr ${{[0-9]+}}, $[[R0]], 16 |
Daniel Sanders | daf7c02 | 2014-03-31 11:00:04 +0000 | [diff] [blame] | 116 | |
| 117 | ; Don't bother with a MIPS16 version. It's just bswap32 repeated four times and |
| 118 | ; would be very long |
| 119 | |
Raul E. Silvera | a9dafe6 | 2014-03-18 17:49:12 +0000 | [diff] [blame] | 120 | %ret = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %x) |
| 121 | ret <4 x i32> %ret |
| 122 | } |
| 123 | |
Akira Hatanaka | bd95275 | 2011-12-20 23:58:36 +0000 | [diff] [blame] | 124 | declare i32 @llvm.bswap.i32(i32) nounwind readnone |
| 125 | |
| 126 | declare i64 @llvm.bswap.i64(i64) nounwind readnone |
| 127 | |
Raul E. Silvera | a9dafe6 | 2014-03-18 17:49:12 +0000 | [diff] [blame] | 128 | declare <4 x i32> @llvm.bswap.v4i32(<4 x i32>) nounwind readnone |