Ulrich Weigand | 2b3482f | 2017-07-17 17:41:11 +0000 | [diff] [blame] | 1 | ; Test multiplications between an i64 and a sign-extended i16 on z14. |
| 2 | ; |
| 3 | ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s |
| 4 | |
| 5 | declare i64 @foo() |
| 6 | |
| 7 | ; Check MGH with no displacement. |
| 8 | define i64 @f1(i64 %a, i16 *%src) { |
| 9 | ; CHECK-LABEL: f1: |
| 10 | ; CHECK: mgh %r2, 0(%r3) |
| 11 | ; CHECK: br %r14 |
| 12 | %b = load i16, i16 *%src |
| 13 | %bext = sext i16 %b to i64 |
| 14 | %mul = mul i64 %a, %bext |
| 15 | ret i64 %mul |
| 16 | } |
| 17 | |
| 18 | ; Check the high end of the aligned MGH range. |
| 19 | define i64 @f2(i64 %a, i16 *%src) { |
| 20 | ; CHECK-LABEL: f2: |
| 21 | ; CHECK: mgh %r2, 524286(%r3) |
| 22 | ; CHECK: br %r14 |
| 23 | %ptr = getelementptr i16, i16 *%src, i64 262143 |
| 24 | %b = load i16, i16 *%ptr |
| 25 | %bext = sext i16 %b to i64 |
| 26 | %mul = mul i64 %a, %bext |
| 27 | ret i64 %mul |
| 28 | } |
| 29 | |
| 30 | ; Check the next word up, which needs separate address logic. |
| 31 | ; Other sequences besides this one would be OK. |
| 32 | define i64 @f3(i64 %a, i16 *%src) { |
| 33 | ; CHECK-LABEL: f3: |
| 34 | ; CHECK: agfi %r3, 524288 |
| 35 | ; CHECK: mgh %r2, 0(%r3) |
| 36 | ; CHECK: br %r14 |
| 37 | %ptr = getelementptr i16, i16 *%src, i64 262144 |
| 38 | %b = load i16, i16 *%ptr |
| 39 | %bext = sext i16 %b to i64 |
| 40 | %mul = mul i64 %a, %bext |
| 41 | ret i64 %mul |
| 42 | } |
| 43 | |
| 44 | ; Check the high end of the negative aligned MGH range. |
| 45 | define i64 @f4(i64 %a, i16 *%src) { |
| 46 | ; CHECK-LABEL: f4: |
| 47 | ; CHECK: mgh %r2, -2(%r3) |
| 48 | ; CHECK: br %r14 |
| 49 | %ptr = getelementptr i16, i16 *%src, i64 -1 |
| 50 | %b = load i16, i16 *%ptr |
| 51 | %bext = sext i16 %b to i64 |
| 52 | %mul = mul i64 %a, %bext |
| 53 | ret i64 %mul |
| 54 | } |
| 55 | |
| 56 | ; Check the low end of the MGH range. |
| 57 | define i64 @f5(i64 %a, i16 *%src) { |
| 58 | ; CHECK-LABEL: f5: |
| 59 | ; CHECK: mgh %r2, -524288(%r3) |
| 60 | ; CHECK: br %r14 |
| 61 | %ptr = getelementptr i16, i16 *%src, i64 -262144 |
| 62 | %b = load i16, i16 *%ptr |
| 63 | %bext = sext i16 %b to i64 |
| 64 | %mul = mul i64 %a, %bext |
| 65 | ret i64 %mul |
| 66 | } |
| 67 | |
| 68 | ; Check the next word down, which needs separate address logic. |
| 69 | ; Other sequences besides this one would be OK. |
| 70 | define i64 @f6(i64 %a, i16 *%src) { |
| 71 | ; CHECK-LABEL: f6: |
| 72 | ; CHECK: agfi %r3, -524290 |
| 73 | ; CHECK: mgh %r2, 0(%r3) |
| 74 | ; CHECK: br %r14 |
| 75 | %ptr = getelementptr i16, i16 *%src, i64 -262145 |
| 76 | %b = load i16, i16 *%ptr |
| 77 | %bext = sext i16 %b to i64 |
| 78 | %mul = mul i64 %a, %bext |
| 79 | ret i64 %mul |
| 80 | } |
| 81 | |
| 82 | ; Check that MGH allows an index. |
| 83 | define i64 @f7(i64 %a, i64 %src, i64 %index) { |
| 84 | ; CHECK-LABEL: f7: |
| 85 | ; CHECK: mgh %r2, 524284({{%r4,%r3|%r3,%r4}}) |
| 86 | ; CHECK: br %r14 |
| 87 | %add1 = add i64 %src, %index |
| 88 | %add2 = add i64 %add1, 524284 |
| 89 | %ptr = inttoptr i64 %add2 to i16 * |
| 90 | %b = load i16, i16 *%ptr |
| 91 | %bext = sext i16 %b to i64 |
| 92 | %mul = mul i64 %a, %bext |
| 93 | ret i64 %mul |
| 94 | } |
| 95 | |