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gerrit-public.fairphone.software / toolchain / llvm-project / 91be65be656072a68b51a8c4e7bb751ea475d896 / . / llvm / test / CodeGen / X86 / pr35636.ll
blob: a97af6a1ac67fceb027f2541ffe79a6b89f8fe12 [file] [log] [blame]
Simon Pilgrim68f9acc2017-12-12 16:12:53 +0000[diff] [blame]1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
Simon Pilgrimadf72e82018-03-14 21:03:09 +0000[diff] [blame]2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=haswell | FileCheck %s --check-prefix=HSW
3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=znver1 | FileCheck %s --check-prefix=ZN
Simon Pilgrim68f9acc2017-12-12 16:12:53 +0000[diff] [blame]4
5define void @_Z15uint64_to_asciimPc(i64 %arg) {
Simon Pilgrimadf72e82018-03-14 21:03:09 +0000[diff] [blame]6; HSW-LABEL: _Z15uint64_to_asciimPc:
7; HSW: # %bb.0: # %bb
Craig Topperd1c61862018-12-12 21:21:31 +0000[diff] [blame]8; HSW-NEXT: movq %rdi, %rax
9; HSW-NEXT: movabsq $811296384146066817, %rcx # imm = 0xB424DC35095CD81
10; HSW-NEXT: mulq %rcx
11; HSW-NEXT: shrq $42, %rdx
12; HSW-NEXT: imulq $281474977, %rdx, %rax # imm = 0x10C6F7A1
Simon Pilgrimadf72e82018-03-14 21:03:09 +0000[diff] [blame]13; HSW-NEXT: shrq $20, %rax
14; HSW-NEXT: leal (%rax,%rax,4), %eax
15; HSW-NEXT: addl $5, %eax
16; HSW-NEXT: andl $134217727, %eax # imm = 0x7FFFFFF
17; HSW-NEXT: leal (%rax,%rax,4), %eax
18; HSW-NEXT: shrl $26, %eax
19; HSW-NEXT: orb $48, %al
20; HSW-NEXT: movb %al, (%rax)
21; HSW-NEXT: retq
22;
23; ZN-LABEL: _Z15uint64_to_asciimPc:
24; ZN: # %bb.0: # %bb
Craig Topperd1c61862018-12-12 21:21:31 +0000[diff] [blame]25; ZN-NEXT: movq %rdi, %rax
26; ZN-NEXT: movabsq $811296384146066817, %rcx # imm = 0xB424DC35095CD81
27; ZN-NEXT: mulq %rcx
28; ZN-NEXT: shrq $42, %rdx
29; ZN-NEXT: imulq $281474977, %rdx, %rax # imm = 0x10C6F7A1
Simon Pilgrimadf72e82018-03-14 21:03:09 +0000[diff] [blame]30; ZN-NEXT: shrq $20, %rax
31; ZN-NEXT: leal 5(%rax,%rax,4), %eax
32; ZN-NEXT: andl $134217727, %eax # imm = 0x7FFFFFF
33; ZN-NEXT: leal (%rax,%rax,4), %eax
34; ZN-NEXT: shrl $26, %eax
35; ZN-NEXT: orb $48, %al
36; ZN-NEXT: movb %al, (%rax)
37; ZN-NEXT: retq
Simon Pilgrim68f9acc2017-12-12 16:12:53 +0000[diff] [blame]38bb:
39 %tmp = udiv i64 %arg, 100000000000000
40 %tmp1 = mul nuw nsw i64 %tmp, 281474977
41 %tmp2 = lshr i64 %tmp1, 20
42 %tmp3 = trunc i64 %tmp2 to i32
43 %tmp4 = add nuw nsw i32 %tmp3, 1
44 %tmp5 = and i32 %tmp4, 268435455
45 %tmp6 = mul nuw nsw i32 %tmp5, 5
46 %tmp7 = and i32 %tmp6, 134217727
47 %tmp8 = mul nuw nsw i32 %tmp7, 5
48 %tmp9 = lshr i32 %tmp8, 26
49 %tmp10 = trunc i32 %tmp9 to i8
50 %tmp11 = or i8 %tmp10, 48
51 store i8 %tmp11, i8* undef, align 1
52 ret void
53}