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gerrit-public.fairphone.software / toolchain / llvm-project / 91be65be656072a68b51a8c4e7bb751ea475d896 / . / llvm / test / MC / ARM / arm-shift-encoding.s
blob: 3c57b67f6e3ba797db430dab489ad185e77e465e [file] [log] [blame]
Tim Northover0c97e762012-09-22 11:18:12 +0000[diff] [blame]1@ RUN: llvm-mc -mcpu=cortex-a8 -triple armv7 -show-encoding < %s | FileCheck %s
2
3 ldr r0, [r0, r0]
4 ldr r0, [r0, r0, lsr #32]
5 ldr r0, [r0, r0, lsr #16]
6 ldr r0, [r0, r0, lsl #0]
7 ldr r0, [r0, r0, lsl #16]
8 ldr r0, [r0, r0, asr #32]
9 ldr r0, [r0, r0, asr #16]
10 ldr r0, [r0, r0, rrx]
11 ldr r0, [r0, r0, ror #16]
12
13@ CHECK: ldr r0, [r0, r0] @ encoding: [0x00,0x00,0x90,0xe7]
14@ CHECK: ldr r0, [r0, r0, lsr #32] @ encoding: [0x20,0x00,0x90,0xe7]
15@ CHECK: ldr r0, [r0, r0, lsr #16] @ encoding: [0x20,0x08,0x90,0xe7]
16@ CHECK: ldr r0, [r0, r0] @ encoding: [0x00,0x00,0x90,0xe7]
17@ CHECK: ldr r0, [r0, r0, lsl #16] @ encoding: [0x00,0x08,0x90,0xe7]
18@ CHECK: ldr r0, [r0, r0, asr #32] @ encoding: [0x40,0x00,0x90,0xe7]
19@ CHECK: ldr r0, [r0, r0, asr #16] @ encoding: [0x40,0x08,0x90,0xe7]
20@ CHECK: ldr r0, [r0, r0, rrx] @ encoding: [0x60,0x00,0x90,0xe7]
21@ CHECK: ldr r0, [r0, r0, ror #16] @ encoding: [0x60,0x08,0x90,0xe7]
22
23 pld [r0, r0]
24 pld [r0, r0, lsr #32]
25 pld [r0, r0, lsr #16]
26 pld [r0, r0, lsl #0]
27 pld [r0, r0, lsl #16]
28 pld [r0, r0, asr #32]
29 pld [r0, r0, asr #16]
30 pld [r0, r0, rrx]
31 pld [r0, r0, ror #16]
32
33@ CHECK: [r0, r0] @ encoding: [0x00,0xf0,0xd0,0xf7]
34@ CHECK: [r0, r0, lsr #32] @ encoding: [0x20,0xf0,0xd0,0xf7]
35@ CHECK: [r0, r0, lsr #16] @ encoding: [0x20,0xf8,0xd0,0xf7]
36@ CHECK: [r0, r0] @ encoding: [0x00,0xf0,0xd0,0xf7]
37@ CHECK: [r0, r0, lsl #16] @ encoding: [0x00,0xf8,0xd0,0xf7]
38@ CHECK: [r0, r0, asr #32] @ encoding: [0x40,0xf0,0xd0,0xf7]
39@ CHECK: [r0, r0, asr #16] @ encoding: [0x40,0xf8,0xd0,0xf7]
40@ CHECK: [r0, r0, rrx] @ encoding: [0x60,0xf0,0xd0,0xf7]
41@ CHECK: [r0, r0, ror #16] @ encoding: [0x60,0xf8,0xd0,0xf7]
42
43 str r0, [r0, r0]
44 str r0, [r0, r0, lsr #32]
45 str r0, [r0, r0, lsr #16]
46 str r0, [r0, r0, lsl #0]
47 str r0, [r0, r0, lsl #16]
48 str r0, [r0, r0, asr #32]
49 str r0, [r0, r0, asr #16]
50 str r0, [r0, r0, rrx]
51 str r0, [r0, r0, ror #16]
52
53@ CHECK: str r0, [r0, r0] @ encoding: [0x00,0x00,0x80,0xe7]
54@ CHECK: str r0, [r0, r0, lsr #32] @ encoding: [0x20,0x00,0x80,0xe7]
55@ CHECK: str r0, [r0, r0, lsr #16] @ encoding: [0x20,0x08,0x80,0xe7]
56@ CHECK: str r0, [r0, r0] @ encoding: [0x00,0x00,0x80,0xe7]
57@ CHECK: str r0, [r0, r0, lsl #16] @ encoding: [0x00,0x08,0x80,0xe7]
58@ CHECK: str r0, [r0, r0, asr #32] @ encoding: [0x40,0x00,0x80,0xe7]
59@ CHECK: str r0, [r0, r0, asr #16] @ encoding: [0x40,0x08,0x80,0xe7]
60@ CHECK: str r0, [r0, r0, rrx] @ encoding: [0x60,0x00,0x80,0xe7]
61@ CHECK: str r0, [r0, r0, ror #16] @ encoding: [0x60,0x08,0x80,0xe7]
62
63@ Uses printAddrMode2OffsetOperand(), used by LDRBT_POST_IMM LDRBT_POST_REG
64@ LDRB_POST_IMM LDRB_POST_REG LDRT_POST_IMM LDRT_POST_REG LDR_POST_IMM
65@ LDR_POST_REG STRBT_POST_IMM STRBT_POST_REG STRB_POST_IMM STRB_POST_REG
66@ STRT_POST_IMM STRT_POST_REG STR_POST_IMM STR_POST_REG
67
68 ldr r0, [r1], r2, rrx
69 ldr r3, [r4], r5, ror #0
70 str r6, [r7], r8, lsl #0
71 str r9, [r10], r11
72
73@ CHECK: ldr r0, [r1], r2, rrx @ encoding: [0x62,0x00,0x91,0xe6]
74@ CHECK: ldr r3, [r4], r5 @ encoding: [0x05,0x30,0x94,0xe6]
75@ CHECK: str r6, [r7], r8 @ encoding: [0x08,0x60,0x87,0xe6]
76@ CHECK: str r9, [r10], r11 @ encoding: [0x0b,0x90,0x8a,0xe6]
Tim Northover2fdbdc52012-09-22 11:18:19 +0000[diff] [blame]77
78@ Uses printSORegImmOperand(), used by ADCrsi ADDrsi ANDrsi BICrsi EORrsi
79@ ORRrsi RSBrsi RSCrsi SBCrsi SUBrsi CMNzrsi CMPrsi MOVsi MVNsi TEQrsi TSTrsi
80
81 adc sp, lr, pc
82 adc r1, r8, r9, lsr #32
83 adc r2, r7, pc, lsr #16
84 adc r3, r6, r10, lsl #0
85 adc r4, r5, lr, lsl #16
86 adc r5, r4, r11, asr #32
87 adc r6, r3, sp, asr #16
88 adc r7, r2, r12, rrx
89 adc r8, r1, r0, ror #16
90
91@ CHECK: adc sp, lr, pc @ encoding: [0x0f,0xd0,0xae,0xe0]
92@ CHECK: adc r1, r8, r9, lsr #32 @ encoding: [0x29,0x10,0xa8,0xe0]
93@ CHECK: adc r2, r7, pc, lsr #16 @ encoding: [0x2f,0x28,0xa7,0xe0]
94@ CHECK: adc r3, r6, r10 @ encoding: [0x0a,0x30,0xa6,0xe0]
95@ CHECK: adc r4, r5, lr, lsl #16 @ encoding: [0x0e,0x48,0xa5,0xe0]
96@ CHECK: adc r5, r4, r11, asr #32 @ encoding: [0x4b,0x50,0xa4,0xe0]
97@ CHECK: adc r6, r3, sp, asr #16 @ encoding: [0x4d,0x68,0xa3,0xe0]
98@ CHECK: adc r7, r2, r12, rrx @ encoding: [0x6c,0x70,0xa2,0xe0]
99@ CHECK: adc r8, r1, r0, ror #16 @ encoding: [0x60,0x88,0xa1,0xe0]
100
101 cmp sp, lr
102 cmp r1, r8, lsr #32
103 cmp r2, r7, lsr #16
104 cmp r3, r6, lsl #0
105 cmp r4, r5, lsl #16
106 cmp r5, r4, asr #32
107 cmp r6, r3, asr #16
108 cmp r7, r2, rrx
109 cmp r8, r1, ror #16
110
111@ CHECK: cmp sp, lr @ encoding: [0x0e,0x00,0x5d,0xe1]
112@ CHECK: cmp r1, r8, lsr #32 @ encoding: [0x28,0x00,0x51,0xe1]
113@ CHECK: cmp r2, r7, lsr #16 @ encoding: [0x27,0x08,0x52,0xe1]
114@ CHECK: cmp r3, r6 @ encoding: [0x06,0x00,0x53,0xe1]
115@ CHECK: cmp r4, r5, lsl #16 @ encoding: [0x05,0x08,0x54,0xe1]
116@ CHECK: cmp r5, r4, asr #32 @ encoding: [0x44,0x00,0x55,0xe1]
117@ CHECK: cmp r6, r3, asr #16 @ encoding: [0x43,0x08,0x56,0xe1]
118@ CHECK: cmp r7, r2, rrx @ encoding: [0x62,0x00,0x57,0xe1]
119@ CHECK: cmp r8, r1, ror #16 @ encoding: [0x61,0x08,0x58,0xe1]