| Simon Tatham | 3486055 | 2018-11-28 11:43:49 +0000 | [diff] [blame] | 1 | include "llvm/Target/Target.td" |
| 2 | |
| 3 | def TestTarget : Target; |
| 4 | |
| 5 | class Encoding : Instruction { |
| 6 | field bits<8> Inst; |
| 7 | } |
| 8 | |
| 9 | class TestReg<string name, bits<1> enc> : Register<name, []> { |
| 10 | let HWEncoding{15-1} = 0; |
| 11 | let HWEncoding{0} = enc; |
| 12 | } |
| 13 | |
| 14 | def R0 : TestReg<"R0", 0>; |
| 15 | def R1 : TestReg<"R1", 1>; |
| 16 | def Reg : RegisterClass<"TestTarget", [i32], 32, (sequence "R%d", 0, 1)>; |
| 17 | |
| 18 | class TestInstructionWithConstraints<string cstr> : Encoding { |
| 19 | dag OutOperandList = (outs Reg:$dest1, Reg:$dest2); |
| 20 | dag InOperandList = (ins Reg:$src1, Reg:$src2); |
| 21 | string AsmString = "mnemonic $dest1, $dest2, $src1, $src2"; |
| 22 | string AsmVariantName = ""; |
| 23 | let Constraints = cstr; |
| 24 | field bits<1> dest1; |
| 25 | field bits<1> dest2; |
| 26 | field bits<1> src1; |
| 27 | field bits<1> src2; |
| 28 | let Inst{7-4} = 0b1010; |
| 29 | let Inst{3} = dest1{0}; |
| 30 | let Inst{2} = dest2{0}; |
| 31 | let Inst{1} = src1{0}; |
| 32 | let Inst{0} = src2{0}; |
| 33 | } |