| Matt Arsenault | ab41193 | 2018-10-02 03:50:56 +0000 | [diff] [blame] | 1 | ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py |
| 2 | ; RUN: opt -mtriple=amdgcn-amd-amdhsa -S -atomic-expand %s | FileCheck %s |
| 3 | ; RUN: opt -mtriple=r600-mesa-mesa3d -S -atomic-expand %s | FileCheck %s |
| 4 | |
| 5 | define i32 @test_atomicrmw_nand_i32_flat(i32* %ptr, i32 %value) { |
| 6 | ; CHECK-LABEL: @test_atomicrmw_nand_i32_flat( |
| 7 | ; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[PTR:%.*]], align 4 |
| 8 | ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] |
| 9 | ; CHECK: atomicrmw.start: |
| 10 | ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP1]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] |
| 11 | ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[LOADED]], [[VALUE:%.*]] |
| 12 | ; CHECK-NEXT: [[NEW:%.*]] = xor i32 [[TMP2]], -1 |
| 13 | ; CHECK-NEXT: [[TMP3:%.*]] = cmpxchg i32* [[PTR]], i32 [[LOADED]], i32 [[NEW]] seq_cst seq_cst |
| 14 | ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP3]], 1 |
| 15 | ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP3]], 0 |
| 16 | ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] |
| 17 | ; CHECK: atomicrmw.end: |
| 18 | ; CHECK-NEXT: ret i32 [[NEWLOADED]] |
| 19 | ; |
| 20 | %res = atomicrmw nand i32* %ptr, i32 %value seq_cst |
| 21 | ret i32 %res |
| 22 | } |
| 23 | |
| 24 | define i32 @test_atomicrmw_nand_i32_global(i32 addrspace(1)* %ptr, i32 %value) { |
| 25 | ; CHECK-LABEL: @test_atomicrmw_nand_i32_global( |
| 26 | ; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(1)* [[PTR:%.*]], align 4 |
| 27 | ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] |
| 28 | ; CHECK: atomicrmw.start: |
| 29 | ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP1]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] |
| 30 | ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[LOADED]], [[VALUE:%.*]] |
| 31 | ; CHECK-NEXT: [[NEW:%.*]] = xor i32 [[TMP2]], -1 |
| 32 | ; CHECK-NEXT: [[TMP3:%.*]] = cmpxchg i32 addrspace(1)* [[PTR]], i32 [[LOADED]], i32 [[NEW]] seq_cst seq_cst |
| 33 | ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP3]], 1 |
| 34 | ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP3]], 0 |
| 35 | ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] |
| 36 | ; CHECK: atomicrmw.end: |
| 37 | ; CHECK-NEXT: ret i32 [[NEWLOADED]] |
| 38 | ; |
| 39 | %res = atomicrmw nand i32 addrspace(1)* %ptr, i32 %value seq_cst |
| 40 | ret i32 %res |
| 41 | } |
| 42 | |
| 43 | define i32 @test_atomicrmw_nand_i32_local(i32 addrspace(3)* %ptr, i32 %value) { |
| 44 | ; CHECK-LABEL: @test_atomicrmw_nand_i32_local( |
| 45 | ; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(3)* [[PTR:%.*]], align 4 |
| 46 | ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] |
| 47 | ; CHECK: atomicrmw.start: |
| 48 | ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP1]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] |
| 49 | ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[LOADED]], [[VALUE:%.*]] |
| 50 | ; CHECK-NEXT: [[NEW:%.*]] = xor i32 [[TMP2]], -1 |
| 51 | ; CHECK-NEXT: [[TMP3:%.*]] = cmpxchg i32 addrspace(3)* [[PTR]], i32 [[LOADED]], i32 [[NEW]] seq_cst seq_cst |
| 52 | ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP3]], 1 |
| 53 | ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP3]], 0 |
| 54 | ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] |
| 55 | ; CHECK: atomicrmw.end: |
| 56 | ; CHECK-NEXT: ret i32 [[NEWLOADED]] |
| 57 | ; |
| 58 | %res = atomicrmw nand i32 addrspace(3)* %ptr, i32 %value seq_cst |
| 59 | ret i32 %res |
| 60 | } |