blob: 79f3fa08fda45bebe275e5dd617225e5cbc9b45e [file] [log] [blame]
Sanjoy Das0e643db2018-04-26 20:52:27 +00001; RUN: opt < %s -instcombine -S | FileCheck %s
2; ModuleID = 'test/Transforms/InstCombine/add4.ll'
3source_filename = "test/Transforms/InstCombine/add4.ll"
4
5define i64 @match_unsigned(i64 %x) {
6; CHECK-LABEL: @match_unsigned(
Sanjoy Das6f1937b2018-04-26 20:52:28 +00007; CHECK-NEXT: bb:
8; CHECK-NEXT: [[UREM:%.*]] = urem i64 [[X:%.*]], 19136
9; CHECK-NEXT: ret i64 [[UREM]]
Sanjoy Das0e643db2018-04-26 20:52:27 +000010;
11bb:
12 %tmp = urem i64 %x, 299
13 %tmp1 = udiv i64 %x, 299
14 %tmp2 = urem i64 %tmp1, 64
15 %tmp3 = mul i64 %tmp2, 299
Sanjoy Das6f1937b2018-04-26 20:52:28 +000016 %tmp4 = add i64 %tmp, %tmp3
Sanjoy Das0e643db2018-04-26 20:52:27 +000017 ret i64 %tmp4
18}
19
20define i64 @match_andAsRem_lshrAsDiv_shlAsMul(i64 %x) {
21; CHECK-LABEL: @match_andAsRem_lshrAsDiv_shlAsMul(
Sanjoy Das6f1937b2018-04-26 20:52:28 +000022; CHECK-NEXT: bb:
23; CHECK-NEXT: [[UREM:%.*]] = urem i64 [[X:%.*]], 576
24; CHECK-NEXT: ret i64 [[UREM]]
Sanjoy Das0e643db2018-04-26 20:52:27 +000025;
26bb:
27 %tmp = and i64 %x, 63
28 %tmp1 = lshr i64 %x, 6
29 %tmp2 = urem i64 %tmp1, 9
Sanjoy Das6f1937b2018-04-26 20:52:28 +000030 %tmp3 = shl i64 %tmp2, 6
31 %tmp4 = add i64 %tmp, %tmp3
Sanjoy Das0e643db2018-04-26 20:52:27 +000032 ret i64 %tmp4
33}
34
35define i64 @match_signed(i64 %x) {
36; CHECK-LABEL: @match_signed(
Sanjoy Das6f1937b2018-04-26 20:52:28 +000037; CHECK-NEXT: bb:
38; CHECK-NEXT: [[SREM1:%.*]] = srem i64 [[X:%.*]], 172224
39; CHECK-NEXT: ret i64 [[SREM1]]
Sanjoy Das0e643db2018-04-26 20:52:27 +000040;
41bb:
42 %tmp = srem i64 %x, 299
43 %tmp1 = sdiv i64 %x, 299
44 %tmp2 = srem i64 %tmp1, 64
45 %tmp3 = sdiv i64 %x, 19136
46 %tmp4 = srem i64 %tmp3, 9
Sanjoy Das6f1937b2018-04-26 20:52:28 +000047 %tmp5 = mul i64 %tmp2, 299
48 %tmp6 = add i64 %tmp, %tmp5
49 %tmp7 = mul i64 %tmp4, 19136
50 %tmp8 = add i64 %tmp6, %tmp7
Sanjoy Das0e643db2018-04-26 20:52:27 +000051 ret i64 %tmp8
52}
53
54define i64 @not_match_inconsistent_signs(i64 %x) {
55; CHECK-LABEL: @not_match_inconsistent_signs(
Sanjoy Das6f1937b2018-04-26 20:52:28 +000056; CHECK: [[TMP:%.*]] = add
Sanjoy Das0e643db2018-04-26 20:52:27 +000057; CHECK-NEXT: ret i64 [[TMP]]
58;
59bb:
60 %tmp = urem i64 %x, 299
61 %tmp1 = sdiv i64 %x, 299
62 %tmp2 = urem i64 %tmp1, 64
63 %tmp3 = mul i64 %tmp2, 299
Sanjoy Das6f1937b2018-04-26 20:52:28 +000064 %tmp4 = add i64 %tmp, %tmp3
Sanjoy Das0e643db2018-04-26 20:52:27 +000065 ret i64 %tmp4
66}
67
68define i64 @not_match_inconsistent_values(i64 %x) {
69; CHECK-LABEL: @not_match_inconsistent_values(
Sanjoy Das6f1937b2018-04-26 20:52:28 +000070; CHECK: [[TMP:%.*]] = add
Sanjoy Das0e643db2018-04-26 20:52:27 +000071; CHECK-NEXT: ret i64 [[TMP]]
72;
73bb:
74 %tmp = urem i64 %x, 299
75 %tmp1 = udiv i64 %x, 29
76 %tmp2 = urem i64 %tmp1, 64
77 %tmp3 = mul i64 %tmp2, 299
Sanjoy Das6f1937b2018-04-26 20:52:28 +000078 %tmp4 = add i64 %tmp, %tmp3
Sanjoy Das0e643db2018-04-26 20:52:27 +000079 ret i64 %tmp4
80}
Sanjoy Das6f1937b2018-04-26 20:52:28 +000081
82define i32 @not_match_overflow(i32 %x) {
83; CHECK-LABEL: @not_match_overflow(
84; CHECK: [[TMP:%.*]] = add
85; CHECK-NEXT: ret i32 [[TMP]]
86;
87bb:
88 %tmp = urem i32 %x, 299
89 %tmp1 = udiv i32 %x,299
90 %tmp2 = urem i32 %tmp1, 147483647
91 %tmp3 = mul i32 %tmp2, 299
92 %tmp4 = add i32 %tmp, %tmp3
93 ret i32 %tmp4
94}