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gerrit-public.fairphone.software / toolchain / llvm-project / 612d693c64ce3e53854f0ecd92210515c5036977 / . / llvm / lib / Target / AArch64 / Disassembler / AArch64Disassembler.cpp
blob: 73db32c048712ec8a956c62483be09bd7bc97812 [file] [log] [blame]
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1//===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===//
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10//
11//===----------------------------------------------------------------------===//
12
13#include "AArch64Disassembler.h"
14#include "AArch64ExternalSymbolizer.h"
15#include "AArch64Subtarget.h"
16#include "MCTargetDesc/AArch64AddressingModes.h"
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]17#include "MCTargetDesc/AArch64MCTargetDesc.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]18#include "Utils/AArch64BaseInfo.h"
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]19#include "llvm-c/Disassembler.h"
20#include "llvm/MC/MCDisassembler/MCRelocationInfo.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]21#include "llvm/MC/MCFixedLenDisassembler.h"
Benjamin Kramer1f8930e2014-07-25 11:42:14 +0000[diff] [blame]22#include "llvm/MC/MCInst.h"
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]23#include "llvm/Support/Compiler.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]24#include "llvm/Support/Debug.h"
Benjamin Kramer1f8930e2014-07-25 11:42:14 +0000[diff] [blame]25#include "llvm/Support/ErrorHandling.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]26#include "llvm/Support/TargetRegistry.h"
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]27#include <algorithm>
28#include <memory>
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]29
30using namespace llvm;
31
32#define DEBUG_TYPE "aarch64-disassembler"
33
34// Pull DecodeStatus and its enum values into the global namespace.
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]35using DecodeStatus = MCDisassembler::DecodeStatus;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]36
37// Forward declare these because the autogenerated code will reference them.
38// Definitions are further down.
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]39static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]40 unsigned RegNo, uint64_t Address,
41 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]42static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]43 unsigned RegNo,
44 uint64_t Address,
45 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]46static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]47 uint64_t Address,
48 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]49static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]50 uint64_t Address,
51 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]52static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]53 uint64_t Address,
54 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]55static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]56 uint64_t Address,
57 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]58static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]59 uint64_t Address,
60 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]61static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]62 unsigned RegNo, uint64_t Address,
63 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]64static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]65 uint64_t Address,
66 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]67static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]68 unsigned RegNo, uint64_t Address,
69 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]70static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]71 uint64_t Address,
72 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]73static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]74 uint64_t Address,
75 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]76static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]77 uint64_t Address,
78 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]79static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]80 uint64_t Address,
81 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]82static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]83 uint64_t Address,
84 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]85static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]86 uint64_t Address,
87 const void *Decoder);
88
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]89static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]90 uint64_t Address,
91 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]92static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]93 uint64_t Address,
94 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]95static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]96 uint64_t Address, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]97static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]98 uint64_t Address, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]99static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]100 uint64_t Address, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]101static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]102 uint64_t Address, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]103static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]104 uint64_t Address,
105 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]106static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]107 uint64_t Address,
108 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]109static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]110 uint64_t Address,
111 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]112static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
113 uint64_t Address,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]114 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]115static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]116 uint64_t Address,
117 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]118static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]119 uint64_t Address,
120 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]121static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
122 uint64_t Address,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]123 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]124static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn,
125 uint64_t Address,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]126 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]127static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]128 uint64_t Address,
129 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]130static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn,
131 uint64_t Address,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]132 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]133static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]134 uint64_t Address, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]135static DecodeStatus DecodeBaseAddSubImm(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]136 uint64_t Address, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]137static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]138 uint64_t Address,
139 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]140static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]141 uint64_t Address,
142 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]143static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]144 uint64_t Address, const void *Decoder);
145
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]146static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]147 uint64_t Address,
148 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]149static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]150 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]151static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]152 uint64_t Addr,
153 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]154static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]155 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]156static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]157 uint64_t Addr,
158 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]159static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]160 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]161static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]162 uint64_t Addr,
163 const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]164static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]165 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]166static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]167 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]168static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]169 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]170static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]171 uint64_t Addr, const void *Decoder);
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]172static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]173 uint64_t Addr, const void *Decoder);
Vladimir Sukharev5f6f60d2015-06-02 10:58:41 +0000[diff] [blame]174static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst,
175 unsigned RegNo,
176 uint64_t Addr,
177 const void *Decoder);
178static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst,
179 unsigned RegNo,
180 uint64_t Addr,
181 const void *Decoder);
Sam Parker6d42de72017-08-11 13:14:00 +0000[diff] [blame]182template<int Bits>
183static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm,
184 uint64_t Address, const void *Decoder);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]185
186static bool Check(DecodeStatus &Out, DecodeStatus In) {
187 switch (In) {
188 case MCDisassembler::Success:
189 // Out stays the same.
190 return true;
191 case MCDisassembler::SoftFail:
192 Out = In;
193 return true;
194 case MCDisassembler::Fail:
195 Out = In;
196 return false;
197 }
198 llvm_unreachable("Invalid DecodeStatus!");
199}
200
201#include "AArch64GenDisassemblerTables.inc"
202#include "AArch64GenInstrInfo.inc"
203
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]204#define Success MCDisassembler::Success
205#define Fail MCDisassembler::Fail
206#define SoftFail MCDisassembler::SoftFail
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]207
208static MCDisassembler *createAArch64Disassembler(const Target &T,
209 const MCSubtargetInfo &STI,
210 MCContext &Ctx) {
211 return new AArch64Disassembler(STI, Ctx);
212}
213
214DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size,
Rafael Espindola7fc5b872014-11-12 02:04:27 +0000[diff] [blame]215 ArrayRef<uint8_t> Bytes,
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000[diff] [blame]216 uint64_t Address,
217 raw_ostream &OS,
218 raw_ostream &CS) const {
219 CommentStream = &CS;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]220
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]221 Size = 0;
222 // We want to read exactly 4 bytes of data.
Rafael Espindola7fc5b872014-11-12 02:04:27 +0000[diff] [blame]223 if (Bytes.size() < 4)
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]224 return Fail;
225 Size = 4;
226
227 // Encoded as a small-endian 32-bit word in the stream.
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000[diff] [blame]228 uint32_t Insn =
229 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]230
231 // Calling the auto-generated decoder function.
Rafael Espindola4aa6bea2014-11-10 18:11:10 +0000[diff] [blame]232 return decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]233}
234
Daniel Sanders50f17232015-09-15 16:17:27 +0000[diff] [blame]235static MCSymbolizer *
236createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo,
237 LLVMSymbolLookupCallback SymbolLookUp,
238 void *DisInfo, MCContext *Ctx,
239 std::unique_ptr<MCRelocationInfo> &&RelInfo) {
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]240 return new AArch64ExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo,
241 SymbolLookUp, DisInfo);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]242}
243
244extern "C" void LLVMInitializeAArch64Disassembler() {
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]245 TargetRegistry::RegisterMCDisassembler(getTheAArch64leTarget(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]246 createAArch64Disassembler);
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]247 TargetRegistry::RegisterMCDisassembler(getTheAArch64beTarget(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]248 createAArch64Disassembler);
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]249 TargetRegistry::RegisterMCSymbolizer(getTheAArch64leTarget(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]250 createAArch64ExternalSymbolizer);
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]251 TargetRegistry::RegisterMCSymbolizer(getTheAArch64beTarget(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]252 createAArch64ExternalSymbolizer);
253
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]254 TargetRegistry::RegisterMCDisassembler(getTheARM64Target(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]255 createAArch64Disassembler);
Mehdi Aminif42454b2016-10-09 23:00:34 +0000[diff] [blame]256 TargetRegistry::RegisterMCSymbolizer(getTheARM64Target(),
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]257 createAArch64ExternalSymbolizer);
258}
259
260static const unsigned FPR128DecoderTable[] = {
261 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
262 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9,
263 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14,
264 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19,
265 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
266 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29,
267 AArch64::Q30, AArch64::Q31
268};
269
270static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo,
271 uint64_t Addr,
272 const void *Decoder) {
273 if (RegNo > 31)
274 return Fail;
275
276 unsigned Register = FPR128DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]277 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]278 return Success;
279}
280
281static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo,
282 uint64_t Addr,
283 const void *Decoder) {
284 if (RegNo > 15)
285 return Fail;
286 return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder);
287}
288
289static const unsigned FPR64DecoderTable[] = {
290 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4,
291 AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9,
292 AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14,
293 AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19,
294 AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24,
295 AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29,
296 AArch64::D30, AArch64::D31
297};
298
299static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
300 uint64_t Addr,
301 const void *Decoder) {
302 if (RegNo > 31)
303 return Fail;
304
305 unsigned Register = FPR64DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]306 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]307 return Success;
308}
309
310static const unsigned FPR32DecoderTable[] = {
311 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4,
312 AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9,
313 AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14,
314 AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19,
315 AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24,
316 AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29,
317 AArch64::S30, AArch64::S31
318};
319
320static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
321 uint64_t Addr,
322 const void *Decoder) {
323 if (RegNo > 31)
324 return Fail;
325
326 unsigned Register = FPR32DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]327 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]328 return Success;
329}
330
331static const unsigned FPR16DecoderTable[] = {
332 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4,
333 AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9,
334 AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14,
335 AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19,
336 AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24,
337 AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29,
338 AArch64::H30, AArch64::H31
339};
340
341static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
342 uint64_t Addr,
343 const void *Decoder) {
344 if (RegNo > 31)
345 return Fail;
346
347 unsigned Register = FPR16DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]348 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]349 return Success;
350}
351
352static const unsigned FPR8DecoderTable[] = {
353 AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4,
354 AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9,
355 AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14,
356 AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19,
357 AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24,
358 AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29,
359 AArch64::B30, AArch64::B31
360};
361
362static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
363 uint64_t Addr,
364 const void *Decoder) {
365 if (RegNo > 31)
366 return Fail;
367
368 unsigned Register = FPR8DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]369 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]370 return Success;
371}
372
373static const unsigned GPR64DecoderTable[] = {
374 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4,
375 AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9,
376 AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14,
377 AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19,
378 AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24,
379 AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP,
380 AArch64::LR, AArch64::XZR
381};
382
383static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
384 uint64_t Addr,
385 const void *Decoder) {
386 if (RegNo > 31)
387 return Fail;
388
389 unsigned Register = GPR64DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]390 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]391 return Success;
392}
393
394static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo,
395 uint64_t Addr,
396 const void *Decoder) {
397 if (RegNo > 31)
398 return Fail;
399 unsigned Register = GPR64DecoderTable[RegNo];
400 if (Register == AArch64::XZR)
401 Register = AArch64::SP;
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]402 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]403 return Success;
404}
405
406static const unsigned GPR32DecoderTable[] = {
407 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4,
408 AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9,
409 AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14,
410 AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19,
411 AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24,
412 AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29,
413 AArch64::W30, AArch64::WZR
414};
415
416static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
417 uint64_t Addr,
418 const void *Decoder) {
419 if (RegNo > 31)
420 return Fail;
421
422 unsigned Register = GPR32DecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]423 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]424 return Success;
425}
426
427static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo,
428 uint64_t Addr,
429 const void *Decoder) {
430 if (RegNo > 31)
431 return Fail;
432
433 unsigned Register = GPR32DecoderTable[RegNo];
434 if (Register == AArch64::WZR)
435 Register = AArch64::WSP;
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]436 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]437 return Success;
438}
439
440static const unsigned VectorDecoderTable[] = {
441 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
442 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9,
443 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14,
444 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19,
445 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
446 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29,
447 AArch64::Q30, AArch64::Q31
448};
449
450static DecodeStatus DecodeVectorRegisterClass(MCInst &Inst, unsigned RegNo,
451 uint64_t Addr,
452 const void *Decoder) {
453 if (RegNo > 31)
454 return Fail;
455
456 unsigned Register = VectorDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]457 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]458 return Success;
459}
460
461static const unsigned QQDecoderTable[] = {
462 AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4,
463 AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8,
464 AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12,
465 AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16,
466 AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20,
467 AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24,
468 AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28,
469 AArch64::Q28_Q29, AArch64::Q29_Q30, AArch64::Q30_Q31, AArch64::Q31_Q0
470};
471
472static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
473 uint64_t Addr, const void *Decoder) {
474 if (RegNo > 31)
475 return Fail;
476 unsigned Register = QQDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]477 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]478 return Success;
479}
480
481static const unsigned QQQDecoderTable[] = {
482 AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4,
483 AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7,
484 AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10,
485 AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13,
486 AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16,
487 AArch64::Q15_Q16_Q17, AArch64::Q16_Q17_Q18, AArch64::Q17_Q18_Q19,
488 AArch64::Q18_Q19_Q20, AArch64::Q19_Q20_Q21, AArch64::Q20_Q21_Q22,
489 AArch64::Q21_Q22_Q23, AArch64::Q22_Q23_Q24, AArch64::Q23_Q24_Q25,
490 AArch64::Q24_Q25_Q26, AArch64::Q25_Q26_Q27, AArch64::Q26_Q27_Q28,
491 AArch64::Q27_Q28_Q29, AArch64::Q28_Q29_Q30, AArch64::Q29_Q30_Q31,
492 AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1
493};
494
495static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
496 uint64_t Addr, const void *Decoder) {
497 if (RegNo > 31)
498 return Fail;
499 unsigned Register = QQQDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]500 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]501 return Success;
502}
503
504static const unsigned QQQQDecoderTable[] = {
505 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5,
506 AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8,
507 AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11,
508 AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14,
509 AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17,
510 AArch64::Q15_Q16_Q17_Q18, AArch64::Q16_Q17_Q18_Q19, AArch64::Q17_Q18_Q19_Q20,
511 AArch64::Q18_Q19_Q20_Q21, AArch64::Q19_Q20_Q21_Q22, AArch64::Q20_Q21_Q22_Q23,
512 AArch64::Q21_Q22_Q23_Q24, AArch64::Q22_Q23_Q24_Q25, AArch64::Q23_Q24_Q25_Q26,
513 AArch64::Q24_Q25_Q26_Q27, AArch64::Q25_Q26_Q27_Q28, AArch64::Q26_Q27_Q28_Q29,
514 AArch64::Q27_Q28_Q29_Q30, AArch64::Q28_Q29_Q30_Q31, AArch64::Q29_Q30_Q31_Q0,
515 AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2
516};
517
518static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
519 uint64_t Addr,
520 const void *Decoder) {
521 if (RegNo > 31)
522 return Fail;
523 unsigned Register = QQQQDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]524 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]525 return Success;
526}
527
528static const unsigned DDDecoderTable[] = {
529 AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4,
530 AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8,
531 AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12,
532 AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16,
533 AArch64::D16_D17, AArch64::D17_D18, AArch64::D18_D19, AArch64::D19_D20,
534 AArch64::D20_D21, AArch64::D21_D22, AArch64::D22_D23, AArch64::D23_D24,
535 AArch64::D24_D25, AArch64::D25_D26, AArch64::D26_D27, AArch64::D27_D28,
536 AArch64::D28_D29, AArch64::D29_D30, AArch64::D30_D31, AArch64::D31_D0
537};
538
539static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
540 uint64_t Addr, const void *Decoder) {
541 if (RegNo > 31)
542 return Fail;
543 unsigned Register = DDDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]544 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]545 return Success;
546}
547
548static const unsigned DDDDecoderTable[] = {
549 AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4,
550 AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7,
551 AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10,
552 AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13,
553 AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16,
554 AArch64::D15_D16_D17, AArch64::D16_D17_D18, AArch64::D17_D18_D19,
555 AArch64::D18_D19_D20, AArch64::D19_D20_D21, AArch64::D20_D21_D22,
556 AArch64::D21_D22_D23, AArch64::D22_D23_D24, AArch64::D23_D24_D25,
557 AArch64::D24_D25_D26, AArch64::D25_D26_D27, AArch64::D26_D27_D28,
558 AArch64::D27_D28_D29, AArch64::D28_D29_D30, AArch64::D29_D30_D31,
559 AArch64::D30_D31_D0, AArch64::D31_D0_D1
560};
561
562static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
563 uint64_t Addr, const void *Decoder) {
564 if (RegNo > 31)
565 return Fail;
566 unsigned Register = DDDDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]567 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]568 return Success;
569}
570
571static const unsigned DDDDDecoderTable[] = {
572 AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5,
573 AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8,
574 AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11,
575 AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14,
576 AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17,
577 AArch64::D15_D16_D17_D18, AArch64::D16_D17_D18_D19, AArch64::D17_D18_D19_D20,
578 AArch64::D18_D19_D20_D21, AArch64::D19_D20_D21_D22, AArch64::D20_D21_D22_D23,
579 AArch64::D21_D22_D23_D24, AArch64::D22_D23_D24_D25, AArch64::D23_D24_D25_D26,
580 AArch64::D24_D25_D26_D27, AArch64::D25_D26_D27_D28, AArch64::D26_D27_D28_D29,
581 AArch64::D27_D28_D29_D30, AArch64::D28_D29_D30_D31, AArch64::D29_D30_D31_D0,
582 AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2
583};
584
585static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
586 uint64_t Addr,
587 const void *Decoder) {
588 if (RegNo > 31)
589 return Fail;
590 unsigned Register = DDDDDecoderTable[RegNo];
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]591 Inst.addOperand(MCOperand::createReg(Register));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]592 return Success;
593}
594
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]595static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]596 uint64_t Addr,
597 const void *Decoder) {
598 // scale{5} is asserted as 1 in tblgen.
Tom Coxon2c13e712014-09-30 16:23:16 +0000[diff] [blame]599 Imm |= 0x20;
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]600 Inst.addOperand(MCOperand::createImm(64 - Imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]601 return Success;
602}
603
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]604static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]605 uint64_t Addr,
606 const void *Decoder) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]607 Inst.addOperand(MCOperand::createImm(64 - Imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]608 return Success;
609}
610
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]611static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]612 uint64_t Addr, const void *Decoder) {
613 int64_t ImmVal = Imm;
614 const AArch64Disassembler *Dis =
615 static_cast<const AArch64Disassembler *>(Decoder);
616
617 // Sign-extend 19-bit immediate.
618 if (ImmVal & (1 << (19 - 1)))
619 ImmVal |= ~((1LL << 19) - 1);
620
Alexey Samsonov729b12e2014-09-02 16:19:41 +0000[diff] [blame]621 if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal * 4, Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]622 Inst.getOpcode() != AArch64::LDRXl, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]623 Inst.addOperand(MCOperand::createImm(ImmVal));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]624 return Success;
625}
626
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]627static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]628 uint64_t Address, const void *Decoder) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]629 Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1));
630 Inst.addOperand(MCOperand::createImm(Imm & 1));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]631 return Success;
632}
633
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]634static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]635 uint64_t Address,
636 const void *Decoder) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]637 Inst.addOperand(MCOperand::createImm(Imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]638
Tom Coxone493f172014-10-01 10:13:59 +0000[diff] [blame]639 // Every system register in the encoding space is valid with the syntax
640 // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds.
641 return Success;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]642}
643
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]644static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]645 uint64_t Address,
646 const void *Decoder) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]647 Inst.addOperand(MCOperand::createImm(Imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]648
Tom Coxone493f172014-10-01 10:13:59 +0000[diff] [blame]649 return Success;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]650}
651
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]652static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]653 uint64_t Address,
654 const void *Decoder) {
655 // This decoder exists to add the dummy Lane operand to the MCInst, which must
656 // be 1 in assembly but has no other real manifestation.
657 unsigned Rd = fieldFromInstruction(Insn, 0, 5);
658 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
659 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
660
661 if (IsToVec) {
662 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
663 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
664 } else {
665 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
666 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
667 }
668
669 // Add the lane
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]670 Inst.addOperand(MCOperand::createImm(1));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]671
672 return Success;
673}
674
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]675static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]676 unsigned Add) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]677 Inst.addOperand(MCOperand::createImm(Add - Imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]678 return Success;
679}
680
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]681static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]682 unsigned Add) {
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]683 Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1)));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]684 return Success;
685}
686
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]687static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]688 uint64_t Addr, const void *Decoder) {
689 return DecodeVecShiftRImm(Inst, Imm, 64);
690}
691
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]692static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]693 uint64_t Addr,
694 const void *Decoder) {
695 return DecodeVecShiftRImm(Inst, Imm | 0x20, 64);
696}
697
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]698static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]699 uint64_t Addr, const void *Decoder) {
700 return DecodeVecShiftRImm(Inst, Imm, 32);
701}
702
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]703static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]704 uint64_t Addr,
705 const void *Decoder) {
706 return DecodeVecShiftRImm(Inst, Imm | 0x10, 32);
707}
708
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]709static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]710 uint64_t Addr, const void *Decoder) {
711 return DecodeVecShiftRImm(Inst, Imm, 16);
712}
713
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]714static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]715 uint64_t Addr,
716 const void *Decoder) {
717 return DecodeVecShiftRImm(Inst, Imm | 0x8, 16);
718}
719
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]720static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]721 uint64_t Addr, const void *Decoder) {
722 return DecodeVecShiftRImm(Inst, Imm, 8);
723}
724
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]725static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]726 uint64_t Addr, const void *Decoder) {
727 return DecodeVecShiftLImm(Inst, Imm, 64);
728}
729
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]730static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]731 uint64_t Addr, const void *Decoder) {
732 return DecodeVecShiftLImm(Inst, Imm, 32);
733}
734
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]735static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]736 uint64_t Addr, const void *Decoder) {
737 return DecodeVecShiftLImm(Inst, Imm, 16);
738}
739
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]740static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]741 uint64_t Addr, const void *Decoder) {
742 return DecodeVecShiftLImm(Inst, Imm, 8);
743}
744
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]745static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn,
746 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]747 const void *Decoder) {
748 unsigned Rd = fieldFromInstruction(insn, 0, 5);
749 unsigned Rn = fieldFromInstruction(insn, 5, 5);
750 unsigned Rm = fieldFromInstruction(insn, 16, 5);
751 unsigned shiftHi = fieldFromInstruction(insn, 22, 2);
752 unsigned shiftLo = fieldFromInstruction(insn, 10, 6);
753 unsigned shift = (shiftHi << 6) | shiftLo;
754 switch (Inst.getOpcode()) {
755 default:
756 return Fail;
757 case AArch64::ADDWrs:
758 case AArch64::ADDSWrs:
759 case AArch64::SUBWrs:
760 case AArch64::SUBSWrs:
761 // if shift == '11' then ReservedValue()
762 if (shiftHi == 0x3)
763 return Fail;
Simon Pilgrimcb07d672017-07-07 16:40:06 +0000[diff] [blame]764 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]765 case AArch64::ANDWrs:
766 case AArch64::ANDSWrs:
767 case AArch64::BICWrs:
768 case AArch64::BICSWrs:
769 case AArch64::ORRWrs:
770 case AArch64::ORNWrs:
771 case AArch64::EORWrs:
772 case AArch64::EONWrs: {
773 // if sf == '0' and imm6<5> == '1' then ReservedValue()
774 if (shiftLo >> 5 == 1)
775 return Fail;
776 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
777 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
778 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
779 break;
780 }
781 case AArch64::ADDXrs:
782 case AArch64::ADDSXrs:
783 case AArch64::SUBXrs:
784 case AArch64::SUBSXrs:
785 // if shift == '11' then ReservedValue()
786 if (shiftHi == 0x3)
787 return Fail;
Simon Pilgrimcb07d672017-07-07 16:40:06 +0000[diff] [blame]788 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]789 case AArch64::ANDXrs:
790 case AArch64::ANDSXrs:
791 case AArch64::BICXrs:
792 case AArch64::BICSXrs:
793 case AArch64::ORRXrs:
794 case AArch64::ORNXrs:
795 case AArch64::EORXrs:
796 case AArch64::EONXrs:
797 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
798 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
799 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
800 break;
801 }
802
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]803 Inst.addOperand(MCOperand::createImm(shift));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]804 return Success;
805}
806
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]807static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]808 uint64_t Addr,
809 const void *Decoder) {
810 unsigned Rd = fieldFromInstruction(insn, 0, 5);
811 unsigned imm = fieldFromInstruction(insn, 5, 16);
812 unsigned shift = fieldFromInstruction(insn, 21, 2);
813 shift <<= 4;
814 switch (Inst.getOpcode()) {
815 default:
816 return Fail;
817 case AArch64::MOVZWi:
818 case AArch64::MOVNWi:
819 case AArch64::MOVKWi:
820 if (shift & (1U << 5))
821 return Fail;
822 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
823 break;
824 case AArch64::MOVZXi:
825 case AArch64::MOVNXi:
826 case AArch64::MOVKXi:
827 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
828 break;
829 }
830
831 if (Inst.getOpcode() == AArch64::MOVKWi ||
832 Inst.getOpcode() == AArch64::MOVKXi)
833 Inst.addOperand(Inst.getOperand(0));
834
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]835 Inst.addOperand(MCOperand::createImm(imm));
836 Inst.addOperand(MCOperand::createImm(shift));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]837 return Success;
838}
839
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]840static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn,
841 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]842 const void *Decoder) {
843 unsigned Rt = fieldFromInstruction(insn, 0, 5);
844 unsigned Rn = fieldFromInstruction(insn, 5, 5);
845 unsigned offset = fieldFromInstruction(insn, 10, 12);
846 const AArch64Disassembler *Dis =
847 static_cast<const AArch64Disassembler *>(Decoder);
848
849 switch (Inst.getOpcode()) {
850 default:
851 return Fail;
852 case AArch64::PRFMui:
853 // Rt is an immediate in prefetch.
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]854 Inst.addOperand(MCOperand::createImm(Rt));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]855 break;
856 case AArch64::STRBBui:
857 case AArch64::LDRBBui:
858 case AArch64::LDRSBWui:
859 case AArch64::STRHHui:
860 case AArch64::LDRHHui:
861 case AArch64::LDRSHWui:
862 case AArch64::STRWui:
863 case AArch64::LDRWui:
864 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
865 break;
866 case AArch64::LDRSBXui:
867 case AArch64::LDRSHXui:
868 case AArch64::LDRSWui:
869 case AArch64::STRXui:
870 case AArch64::LDRXui:
871 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
872 break;
873 case AArch64::LDRQui:
874 case AArch64::STRQui:
875 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
876 break;
877 case AArch64::LDRDui:
878 case AArch64::STRDui:
879 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
880 break;
881 case AArch64::LDRSui:
882 case AArch64::STRSui:
883 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
884 break;
885 case AArch64::LDRHui:
886 case AArch64::STRHui:
887 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
888 break;
889 case AArch64::LDRBui:
890 case AArch64::STRBui:
891 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
892 break;
893 }
894
895 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
896 if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]897 Inst.addOperand(MCOperand::createImm(offset));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]898 return Success;
899}
900
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]901static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
902 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]903 const void *Decoder) {
904 unsigned Rt = fieldFromInstruction(insn, 0, 5);
905 unsigned Rn = fieldFromInstruction(insn, 5, 5);
906 int64_t offset = fieldFromInstruction(insn, 12, 9);
907
908 // offset is a 9-bit signed immediate, so sign extend it to
909 // fill the unsigned.
910 if (offset & (1 << (9 - 1)))
911 offset |= ~((1LL << 9) - 1);
912
913 // First operand is always the writeback to the address register, if needed.
914 switch (Inst.getOpcode()) {
915 default:
916 break;
917 case AArch64::LDRSBWpre:
918 case AArch64::LDRSHWpre:
919 case AArch64::STRBBpre:
920 case AArch64::LDRBBpre:
921 case AArch64::STRHHpre:
922 case AArch64::LDRHHpre:
923 case AArch64::STRWpre:
924 case AArch64::LDRWpre:
925 case AArch64::LDRSBWpost:
926 case AArch64::LDRSHWpost:
927 case AArch64::STRBBpost:
928 case AArch64::LDRBBpost:
929 case AArch64::STRHHpost:
930 case AArch64::LDRHHpost:
931 case AArch64::STRWpost:
932 case AArch64::LDRWpost:
933 case AArch64::LDRSBXpre:
934 case AArch64::LDRSHXpre:
935 case AArch64::STRXpre:
936 case AArch64::LDRSWpre:
937 case AArch64::LDRXpre:
938 case AArch64::LDRSBXpost:
939 case AArch64::LDRSHXpost:
940 case AArch64::STRXpost:
941 case AArch64::LDRSWpost:
942 case AArch64::LDRXpost:
943 case AArch64::LDRQpre:
944 case AArch64::STRQpre:
945 case AArch64::LDRQpost:
946 case AArch64::STRQpost:
947 case AArch64::LDRDpre:
948 case AArch64::STRDpre:
949 case AArch64::LDRDpost:
950 case AArch64::STRDpost:
951 case AArch64::LDRSpre:
952 case AArch64::STRSpre:
953 case AArch64::LDRSpost:
954 case AArch64::STRSpost:
955 case AArch64::LDRHpre:
956 case AArch64::STRHpre:
957 case AArch64::LDRHpost:
958 case AArch64::STRHpost:
959 case AArch64::LDRBpre:
960 case AArch64::STRBpre:
961 case AArch64::LDRBpost:
962 case AArch64::STRBpost:
963 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
964 break;
965 }
966
967 switch (Inst.getOpcode()) {
968 default:
969 return Fail;
970 case AArch64::PRFUMi:
971 // Rt is an immediate in prefetch.
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]972 Inst.addOperand(MCOperand::createImm(Rt));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]973 break;
974 case AArch64::STURBBi:
975 case AArch64::LDURBBi:
976 case AArch64::LDURSBWi:
977 case AArch64::STURHHi:
978 case AArch64::LDURHHi:
979 case AArch64::LDURSHWi:
980 case AArch64::STURWi:
981 case AArch64::LDURWi:
982 case AArch64::LDTRSBWi:
983 case AArch64::LDTRSHWi:
984 case AArch64::STTRWi:
985 case AArch64::LDTRWi:
986 case AArch64::STTRHi:
987 case AArch64::LDTRHi:
988 case AArch64::LDTRBi:
989 case AArch64::STTRBi:
990 case AArch64::LDRSBWpre:
991 case AArch64::LDRSHWpre:
992 case AArch64::STRBBpre:
993 case AArch64::LDRBBpre:
994 case AArch64::STRHHpre:
995 case AArch64::LDRHHpre:
996 case AArch64::STRWpre:
997 case AArch64::LDRWpre:
998 case AArch64::LDRSBWpost:
999 case AArch64::LDRSHWpost:
1000 case AArch64::STRBBpost:
1001 case AArch64::LDRBBpost:
1002 case AArch64::STRHHpost:
1003 case AArch64::LDRHHpost:
1004 case AArch64::STRWpost:
1005 case AArch64::LDRWpost:
1006 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1007 break;
1008 case AArch64::LDURSBXi:
1009 case AArch64::LDURSHXi:
1010 case AArch64::LDURSWi:
1011 case AArch64::STURXi:
1012 case AArch64::LDURXi:
1013 case AArch64::LDTRSBXi:
1014 case AArch64::LDTRSHXi:
1015 case AArch64::LDTRSWi:
1016 case AArch64::STTRXi:
1017 case AArch64::LDTRXi:
1018 case AArch64::LDRSBXpre:
1019 case AArch64::LDRSHXpre:
1020 case AArch64::STRXpre:
1021 case AArch64::LDRSWpre:
1022 case AArch64::LDRXpre:
1023 case AArch64::LDRSBXpost:
1024 case AArch64::LDRSHXpost:
1025 case AArch64::STRXpost:
1026 case AArch64::LDRSWpost:
1027 case AArch64::LDRXpost:
1028 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1029 break;
1030 case AArch64::LDURQi:
1031 case AArch64::STURQi:
1032 case AArch64::LDRQpre:
1033 case AArch64::STRQpre:
1034 case AArch64::LDRQpost:
1035 case AArch64::STRQpost:
1036 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1037 break;
1038 case AArch64::LDURDi:
1039 case AArch64::STURDi:
1040 case AArch64::LDRDpre:
1041 case AArch64::STRDpre:
1042 case AArch64::LDRDpost:
1043 case AArch64::STRDpost:
1044 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1045 break;
1046 case AArch64::LDURSi:
1047 case AArch64::STURSi:
1048 case AArch64::LDRSpre:
1049 case AArch64::STRSpre:
1050 case AArch64::LDRSpost:
1051 case AArch64::STRSpost:
1052 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1053 break;
1054 case AArch64::LDURHi:
1055 case AArch64::STURHi:
1056 case AArch64::LDRHpre:
1057 case AArch64::STRHpre:
1058 case AArch64::LDRHpost:
1059 case AArch64::STRHpost:
1060 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
1061 break;
1062 case AArch64::LDURBi:
1063 case AArch64::STURBi:
1064 case AArch64::LDRBpre:
1065 case AArch64::STRBpre:
1066 case AArch64::LDRBpost:
1067 case AArch64::STRBpost:
1068 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
1069 break;
1070 }
1071
1072 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1073 Inst.addOperand(MCOperand::createImm(offset));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1074
1075 bool IsLoad = fieldFromInstruction(insn, 22, 1);
1076 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0;
1077 bool IsFP = fieldFromInstruction(insn, 26, 1);
1078
1079 // Cannot write back to a transfer register (but xzr != sp).
1080 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn)
1081 return SoftFail;
1082
1083 return Success;
1084}
1085
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1086static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn,
1087 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1088 const void *Decoder) {
1089 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1090 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1091 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1092 unsigned Rs = fieldFromInstruction(insn, 16, 5);
1093
1094 unsigned Opcode = Inst.getOpcode();
1095 switch (Opcode) {
1096 default:
1097 return Fail;
1098 case AArch64::STLXRW:
1099 case AArch64::STLXRB:
1100 case AArch64::STLXRH:
1101 case AArch64::STXRW:
1102 case AArch64::STXRB:
1103 case AArch64::STXRH:
1104 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1105 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1106 case AArch64::LDARW:
1107 case AArch64::LDARB:
1108 case AArch64::LDARH:
1109 case AArch64::LDAXRW:
1110 case AArch64::LDAXRB:
1111 case AArch64::LDAXRH:
1112 case AArch64::LDXRW:
1113 case AArch64::LDXRB:
1114 case AArch64::LDXRH:
1115 case AArch64::STLRW:
1116 case AArch64::STLRB:
1117 case AArch64::STLRH:
Vladimir Sukharevd49cb8f2015-04-16 15:30:43 +0000[diff] [blame]1118 case AArch64::STLLRW:
1119 case AArch64::STLLRB:
1120 case AArch64::STLLRH:
1121 case AArch64::LDLARW:
1122 case AArch64::LDLARB:
1123 case AArch64::LDLARH:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1124 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1125 break;
1126 case AArch64::STLXRX:
1127 case AArch64::STXRX:
1128 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1129 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1130 case AArch64::LDARX:
1131 case AArch64::LDAXRX:
1132 case AArch64::LDXRX:
1133 case AArch64::STLRX:
Vladimir Sukharevd49cb8f2015-04-16 15:30:43 +0000[diff] [blame]1134 case AArch64::LDLARX:
1135 case AArch64::STLLRX:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1136 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1137 break;
1138 case AArch64::STLXPW:
1139 case AArch64::STXPW:
1140 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1141 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1142 case AArch64::LDAXPW:
1143 case AArch64::LDXPW:
1144 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1145 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1146 break;
1147 case AArch64::STLXPX:
1148 case AArch64::STXPX:
1149 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1150 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1151 case AArch64::LDAXPX:
1152 case AArch64::LDXPX:
1153 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1154 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1155 break;
1156 }
1157
1158 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1159
1160 // You shouldn't load to the same register twice in an instruction...
1161 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW ||
1162 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) &&
1163 Rt == Rt2)
1164 return SoftFail;
1165
1166 return Success;
1167}
1168
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1169static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1170 uint64_t Addr,
1171 const void *Decoder) {
1172 unsigned Rt = fieldFromInstruction(insn, 0, 5);
1173 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1174 unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1175 int64_t offset = fieldFromInstruction(insn, 15, 7);
1176 bool IsLoad = fieldFromInstruction(insn, 22, 1);
1177
1178 // offset is a 7-bit signed immediate, so sign extend it to
1179 // fill the unsigned.
1180 if (offset & (1 << (7 - 1)))
1181 offset |= ~((1LL << 7) - 1);
1182
1183 unsigned Opcode = Inst.getOpcode();
1184 bool NeedsDisjointWritebackTransfer = false;
1185
1186 // First operand is always writeback of base register.
1187 switch (Opcode) {
1188 default:
1189 break;
1190 case AArch64::LDPXpost:
1191 case AArch64::STPXpost:
1192 case AArch64::LDPSWpost:
1193 case AArch64::LDPXpre:
1194 case AArch64::STPXpre:
1195 case AArch64::LDPSWpre:
1196 case AArch64::LDPWpost:
1197 case AArch64::STPWpost:
1198 case AArch64::LDPWpre:
1199 case AArch64::STPWpre:
1200 case AArch64::LDPQpost:
1201 case AArch64::STPQpost:
1202 case AArch64::LDPQpre:
1203 case AArch64::STPQpre:
1204 case AArch64::LDPDpost:
1205 case AArch64::STPDpost:
1206 case AArch64::LDPDpre:
1207 case AArch64::STPDpre:
1208 case AArch64::LDPSpost:
1209 case AArch64::STPSpost:
1210 case AArch64::LDPSpre:
1211 case AArch64::STPSpre:
1212 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1213 break;
1214 }
1215
1216 switch (Opcode) {
1217 default:
1218 return Fail;
1219 case AArch64::LDPXpost:
1220 case AArch64::STPXpost:
1221 case AArch64::LDPSWpost:
1222 case AArch64::LDPXpre:
1223 case AArch64::STPXpre:
1224 case AArch64::LDPSWpre:
1225 NeedsDisjointWritebackTransfer = true;
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1226 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1227 case AArch64::LDNPXi:
1228 case AArch64::STNPXi:
1229 case AArch64::LDPXi:
1230 case AArch64::STPXi:
1231 case AArch64::LDPSWi:
1232 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1233 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1234 break;
1235 case AArch64::LDPWpost:
1236 case AArch64::STPWpost:
1237 case AArch64::LDPWpre:
1238 case AArch64::STPWpre:
1239 NeedsDisjointWritebackTransfer = true;
Justin Bognerb03fd122016-08-17 05:10:15 +0000[diff] [blame]1240 LLVM_FALLTHROUGH;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1241 case AArch64::LDNPWi:
1242 case AArch64::STNPWi:
1243 case AArch64::LDPWi:
1244 case AArch64::STPWi:
1245 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1246 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1247 break;
1248 case AArch64::LDNPQi:
1249 case AArch64::STNPQi:
1250 case AArch64::LDPQpost:
1251 case AArch64::STPQpost:
1252 case AArch64::LDPQi:
1253 case AArch64::STPQi:
1254 case AArch64::LDPQpre:
1255 case AArch64::STPQpre:
1256 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1257 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder);
1258 break;
1259 case AArch64::LDNPDi:
1260 case AArch64::STNPDi:
1261 case AArch64::LDPDpost:
1262 case AArch64::STPDpost:
1263 case AArch64::LDPDi:
1264 case AArch64::STPDi:
1265 case AArch64::LDPDpre:
1266 case AArch64::STPDpre:
1267 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1268 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1269 break;
1270 case AArch64::LDNPSi:
1271 case AArch64::STNPSi:
1272 case AArch64::LDPSpost:
1273 case AArch64::STPSpost:
1274 case AArch64::LDPSi:
1275 case AArch64::STPSi:
1276 case AArch64::LDPSpre:
1277 case AArch64::STPSpre:
1278 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1279 DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1280 break;
1281 }
1282
1283 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1284 Inst.addOperand(MCOperand::createImm(offset));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1285
1286 // You shouldn't load to the same register twice in an instruction...
1287 if (IsLoad && Rt == Rt2)
1288 return SoftFail;
1289
1290 // ... or do any operation that writes-back to a transfer register. But note
1291 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different.
1292 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn))
1293 return SoftFail;
1294
1295 return Success;
1296}
1297
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1298static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
1299 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1300 const void *Decoder) {
1301 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1302 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1303 unsigned Rm = fieldFromInstruction(insn, 16, 5);
1304 unsigned extend = fieldFromInstruction(insn, 10, 6);
1305
1306 unsigned shift = extend & 0x7;
1307 if (shift > 4)
1308 return Fail;
1309
1310 switch (Inst.getOpcode()) {
1311 default:
1312 return Fail;
1313 case AArch64::ADDWrx:
1314 case AArch64::SUBWrx:
1315 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1316 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1317 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1318 break;
1319 case AArch64::ADDSWrx:
1320 case AArch64::SUBSWrx:
1321 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1322 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1323 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1324 break;
1325 case AArch64::ADDXrx:
1326 case AArch64::SUBXrx:
1327 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1328 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1329 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1330 break;
1331 case AArch64::ADDSXrx:
1332 case AArch64::SUBSXrx:
1333 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1334 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1335 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1336 break;
1337 case AArch64::ADDXrx64:
1338 case AArch64::SUBXrx64:
1339 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1340 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1341 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1342 break;
1343 case AArch64::SUBSXrx64:
1344 case AArch64::ADDSXrx64:
1345 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1346 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1347 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1348 break;
1349 }
1350
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1351 Inst.addOperand(MCOperand::createImm(extend));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1352 return Success;
1353}
1354
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1355static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn,
1356 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1357 const void *Decoder) {
1358 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1359 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1360 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1361 unsigned imm;
1362
1363 if (Datasize) {
1364 if (Inst.getOpcode() == AArch64::ANDSXri)
1365 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1366 else
1367 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1368 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
1369 imm = fieldFromInstruction(insn, 10, 13);
1370 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64))
1371 return Fail;
1372 } else {
1373 if (Inst.getOpcode() == AArch64::ANDSWri)
1374 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1375 else
1376 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1377 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
1378 imm = fieldFromInstruction(insn, 10, 12);
1379 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32))
1380 return Fail;
1381 }
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1382 Inst.addOperand(MCOperand::createImm(imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1383 return Success;
1384}
1385
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1386static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1387 uint64_t Addr,
1388 const void *Decoder) {
1389 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1390 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1391 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1392 imm |= fieldFromInstruction(insn, 5, 5);
1393
1394 if (Inst.getOpcode() == AArch64::MOVID)
1395 DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder);
1396 else
1397 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1398
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1399 Inst.addOperand(MCOperand::createImm(imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1400
1401 switch (Inst.getOpcode()) {
1402 default:
1403 break;
1404 case AArch64::MOVIv4i16:
1405 case AArch64::MOVIv8i16:
1406 case AArch64::MVNIv4i16:
1407 case AArch64::MVNIv8i16:
1408 case AArch64::MOVIv2i32:
1409 case AArch64::MOVIv4i32:
1410 case AArch64::MVNIv2i32:
1411 case AArch64::MVNIv4i32:
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1412 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1413 break;
1414 case AArch64::MOVIv2s_msl:
1415 case AArch64::MOVIv4s_msl:
1416 case AArch64::MVNIv2s_msl:
1417 case AArch64::MVNIv4s_msl:
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1418 Inst.addOperand(MCOperand::createImm(cmode & 1 ? 0x110 : 0x108));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1419 break;
1420 }
1421
1422 return Success;
1423}
1424
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1425static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn,
1426 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1427 const void *Decoder) {
1428 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1429 unsigned cmode = fieldFromInstruction(insn, 12, 4);
1430 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1431 imm |= fieldFromInstruction(insn, 5, 5);
1432
1433 // Tied operands added twice.
1434 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1435 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1436
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1437 Inst.addOperand(MCOperand::createImm(imm));
1438 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1439
1440 return Success;
1441}
1442
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1443static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1444 uint64_t Addr, const void *Decoder) {
1445 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1446 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2;
1447 imm |= fieldFromInstruction(insn, 29, 2);
1448 const AArch64Disassembler *Dis =
1449 static_cast<const AArch64Disassembler *>(Decoder);
1450
1451 // Sign-extend the 21-bit immediate.
1452 if (imm & (1 << (21 - 1)))
1453 imm |= ~((1LL << 21) - 1);
1454
1455 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1456 if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1457 Inst.addOperand(MCOperand::createImm(imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1458
1459 return Success;
1460}
1461
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1462static DecodeStatus DecodeBaseAddSubImm(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1463 uint64_t Addr, const void *Decoder) {
1464 unsigned Rd = fieldFromInstruction(insn, 0, 5);
1465 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1466 unsigned Imm = fieldFromInstruction(insn, 10, 14);
1467 unsigned S = fieldFromInstruction(insn, 29, 1);
1468 unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1469
1470 unsigned ShifterVal = (Imm >> 12) & 3;
1471 unsigned ImmVal = Imm & 0xFFF;
1472 const AArch64Disassembler *Dis =
1473 static_cast<const AArch64Disassembler *>(Decoder);
1474
1475 if (ShifterVal != 0 && ShifterVal != 1)
1476 return Fail;
1477
1478 if (Datasize) {
1479 if (Rd == 31 && !S)
1480 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1481 else
1482 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1483 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1484 } else {
1485 if (Rd == 31 && !S)
1486 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1487 else
1488 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1489 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1490 }
1491
1492 if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1493 Inst.addOperand(MCOperand::createImm(ImmVal));
1494 Inst.addOperand(MCOperand::createImm(12 * ShifterVal));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1495 return Success;
1496}
1497
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1498static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1499 uint64_t Addr,
1500 const void *Decoder) {
1501 int64_t imm = fieldFromInstruction(insn, 0, 26);
1502 const AArch64Disassembler *Dis =
1503 static_cast<const AArch64Disassembler *>(Decoder);
1504
1505 // Sign-extend the 26-bit immediate.
1506 if (imm & (1 << (26 - 1)))
1507 imm |= ~((1LL << 26) - 1);
1508
Alexey Samsonov729b12e2014-09-02 16:19:41 +0000[diff] [blame]1509 if (!Dis->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1510 Inst.addOperand(MCOperand::createImm(imm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1511
1512 return Success;
1513}
1514
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1515static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn,
1516 uint64_t Addr,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1517 const void *Decoder) {
1518 uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1519 uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1520 uint64_t crm = fieldFromInstruction(insn, 8, 4);
1521
1522 uint64_t pstate_field = (op1 << 3) | op2;
1523
Oliver Stannard911ea202015-11-26 15:32:30 +0000[diff] [blame]1524 if ((pstate_field == AArch64PState::PAN ||
1525 pstate_field == AArch64PState::UAO) && crm > 1)
Alexandros Lamprineas1bab1912015-10-05 13:42:31 +0000[diff] [blame]1526 return Fail;
1527
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1528 Inst.addOperand(MCOperand::createImm(pstate_field));
1529 Inst.addOperand(MCOperand::createImm(crm));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1530
Tim Northovere6ae6762016-07-05 21:23:04 +0000[diff] [blame]1531 const AArch64Disassembler *Dis =
Vladimir Sukhareva98f6892015-04-16 12:15:27 +0000[diff] [blame]1532 static_cast<const AArch64Disassembler *>(Decoder);
Tim Northovere6ae6762016-07-05 21:23:04 +0000[diff] [blame]1533 auto PState = AArch64PState::lookupPStateByEncoding(pstate_field);
1534 if (PState && PState->haveFeatures(Dis->getSubtargetInfo().getFeatureBits()))
1535 return Success;
1536 return Fail;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1537}
1538
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1539static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1540 uint64_t Addr, const void *Decoder) {
1541 uint64_t Rt = fieldFromInstruction(insn, 0, 5);
1542 uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5;
1543 bit |= fieldFromInstruction(insn, 19, 5);
1544 int64_t dst = fieldFromInstruction(insn, 5, 14);
1545 const AArch64Disassembler *Dis =
1546 static_cast<const AArch64Disassembler *>(Decoder);
1547
1548 // Sign-extend 14-bit immediate.
1549 if (dst & (1 << (14 - 1)))
1550 dst |= ~((1LL << 14) - 1);
1551
1552 if (fieldFromInstruction(insn, 31, 1) == 0)
1553 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1554 else
1555 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1556 Inst.addOperand(MCOperand::createImm(bit));
Alexey Samsonov729b12e2014-09-02 16:19:41 +0000[diff] [blame]1557 if (!Dis->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4))
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]1558 Inst.addOperand(MCOperand::createImm(dst));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1559
1560 return Success;
1561}
Vladimir Sukharev5f6f60d2015-06-02 10:58:41 +0000[diff] [blame]1562
1563static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst,
1564 unsigned RegClassID,
1565 unsigned RegNo,
1566 uint64_t Addr,
1567 const void *Decoder) {
1568 // Register number must be even (see CASP instruction)
1569 if (RegNo & 0x1)
1570 return Fail;
1571
1572 unsigned Register = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo);
1573 Inst.addOperand(MCOperand::createReg(Register));
1574 return Success;
1575}
1576
1577static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst,
1578 unsigned RegNo,
1579 uint64_t Addr,
1580 const void *Decoder) {
Junmo Park45513a82016-07-15 22:42:52 +0000[diff] [blame]1581 return DecodeGPRSeqPairsClassRegisterClass(Inst,
Vladimir Sukharev5f6f60d2015-06-02 10:58:41 +0000[diff] [blame]1582 AArch64::WSeqPairsClassRegClassID,
1583 RegNo, Addr, Decoder);
1584}
1585
1586static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst,
1587 unsigned RegNo,
1588 uint64_t Addr,
1589 const void *Decoder) {
Junmo Park45513a82016-07-15 22:42:52 +0000[diff] [blame]1590 return DecodeGPRSeqPairsClassRegisterClass(Inst,
Vladimir Sukharev5f6f60d2015-06-02 10:58:41 +0000[diff] [blame]1591 AArch64::XSeqPairsClassRegClassID,
1592 RegNo, Addr, Decoder);
1593}
Sam Parker6d42de72017-08-11 13:14:00 +0000[diff] [blame]1594
1595template<int Bits>
1596static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm,
1597 uint64_t Address, const void *Decoder) {
1598 if (Imm & ~((1LL << Bits) - 1))
1599 return Fail;
1600
1601 // Imm is a signed immediate, so sign extend it.
1602 if (Imm & (1 << (Bits - 1)))
1603 Imm |= ~((1LL << Bits) - 1);
1604
1605 Inst.addOperand(MCOperand::createImm(Imm));
1606 return Success;
1607}
1608