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gerrit-public.fairphone.software / toolchain / llvm-project / 92720ab1b2b3b0769ba99d5f0169e927ac0bd4e2 / . / llvm / lib / Target / PowerPC / PPCSchedule440.td
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Jia Liub22310f2012-02-18 12:03:15 +0000[diff] [blame]1//===-- PPCSchedule440.td - PPC 440 Scheduling Definitions -*- tablegen -*-===//
2//
Hal Finkelad677b62011-10-17 04:03:55 +0000[diff] [blame]3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Jia Liub22310f2012-02-18 12:03:15 +0000[diff] [blame]7//
Hal Finkelad677b62011-10-17 04:03:55 +0000[diff] [blame]8//===----------------------------------------------------------------------===//
9
10// Primary reference:
Hal Finkelafa70aa2011-10-17 18:10:08 +0000[diff] [blame]11// PowerPC 440x6 Embedded Processor Core User's Manual.
Hal Finkelad677b62011-10-17 04:03:55 +0000[diff] [blame]12// IBM (as updated in) 2010.
13
14// The basic PPC 440 does not include a floating-point unit; the pipeline
15// timings here are constructed to match the FP2 unit shipped with the
16// PPC-440- and PPC-450-based Blue Gene (L and P) supercomputers.
17// References:
18// S. Chatterjee, et al. Design and exploitation of a high-performance
19// SIMD floating-point unit for Blue Gene/L.
20// IBM J. Res. & Dev. 49 (2/3) March/May 2005.
21// also:
22// Carlos Sosa and Brant Knudson. IBM System Blue Gene Solution:
23// Blue Gene/P Application Development.
24// IBM (as updated in) 2009.
25
26//===----------------------------------------------------------------------===//
27// Functional units on the PowerPC 440/450 chip sets
28//
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]29def P440_IFTH1 : FuncUnit; // Fetch unit 1
30def P440_IFTH2 : FuncUnit; // Fetch unit 2
31def P440_PDCD1 : FuncUnit; // Decode unit 1
32def P440_PDCD2 : FuncUnit; // Decode unit 2
33def P440_DISS1 : FuncUnit; // Issue unit 1
34def P440_DISS2 : FuncUnit; // Issue unit 2
35def P440_LRACC : FuncUnit; // Register access and dispatch for
36 // the simple integer (J-pipe) and
37 // load/store (L-pipe) pipelines
38def P440_IRACC : FuncUnit; // Register access and dispatch for
39 // the complex integer (I-pipe) pipeline
40def P440_FRACC : FuncUnit; // Register access and dispatch for
41 // the floating-point execution (F-pipe) pipeline
42def P440_IEXE1 : FuncUnit; // Execution stage 1 for the I pipeline
43def P440_IEXE2 : FuncUnit; // Execution stage 2 for the I pipeline
44def P440_IWB : FuncUnit; // Write-back unit for the I pipeline
45def P440_JEXE1 : FuncUnit; // Execution stage 1 for the J pipeline
46def P440_JEXE2 : FuncUnit; // Execution stage 2 for the J pipeline
47def P440_JWB : FuncUnit; // Write-back unit for the J pipeline
48def P440_AGEN : FuncUnit; // Address generation for the L pipeline
49def P440_CRD : FuncUnit; // D-cache access for the L pipeline
50def P440_LWB : FuncUnit; // Write-back unit for the L pipeline
51def P440_FEXE1 : FuncUnit; // Execution stage 1 for the F pipeline
52def P440_FEXE2 : FuncUnit; // Execution stage 2 for the F pipeline
53def P440_FEXE3 : FuncUnit; // Execution stage 3 for the F pipeline
54def P440_FEXE4 : FuncUnit; // Execution stage 4 for the F pipeline
55def P440_FEXE5 : FuncUnit; // Execution stage 5 for the F pipeline
56def P440_FEXE6 : FuncUnit; // Execution stage 6 for the F pipeline
57def P440_FWB : FuncUnit; // Write-back unit for the F pipeline
Hal Finkelad677b62011-10-17 04:03:55 +0000[diff] [blame]58
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]59def P440_LWARX_Hold : FuncUnit; // This is a pseudo-unit which is used
60 // to make sure that no lwarx/stwcx.
61 // instructions are issued while another
62 // lwarx/stwcx. is in the L pipe.
Hal Finkelad677b62011-10-17 04:03:55 +0000[diff] [blame]63
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]64def P440_GPR_Bypass : Bypass; // The bypass for general-purpose regs.
65def P440_FPR_Bypass : Bypass; // The bypass for floating-point regs.
Hal Finkelad677b62011-10-17 04:03:55 +0000[diff] [blame]66
67// Notes:
68// Instructions are held in the FRACC, LRACC and IRACC pipeline
69// stages until their source operands become ready. Exceptions:
70// - Store instructions will hold in the AGEN stage
71// - The integer multiply-accumulate instruction will hold in
72// the IEXE1 stage
73//
74// For most I-pipe operations, the result is available at the end of
75// the IEXE1 stage. Operations such as multiply and divide must
76// continue to execute in IEXE2 and IWB. Divide resides in IWB for
77// 33 cycles (multiply also calculates its result in IWB). For all
78// J-pipe instructions, the result is available
79// at the end of the JEXE1 stage. Loads have a 3-cycle latency
80// (data is not available until after the LWB stage).
81//
82// The L1 cache hit latency is four cycles for floating point loads
83// and three cycles for integer loads.
84//
85// The stwcx. instruction requires both the LRACC and the IRACC
86// dispatch stages. It must be issued from DISS0.
87//
88// All lwarx/stwcx. instructions hold in LRACC if another
89// uncommitted lwarx/stwcx. is in AGEN, CRD, or LWB.
90//
91// msync (a.k.a. sync) and mbar will hold in LWB until all load/store
92// resources are empty. AGEN and CRD are held empty until the msync/mbar
93// commits.
94//
95// Most floating-point instructions, computational and move,
96// have a 5-cycle latency. Divide takes longer (30 cycles). Instructions that
97// update the CR take 2 cycles. Stores take 3 cycles and, as mentioned above,
98// loads take 4 cycles (for L1 hit).
99
100//
101// This file defines the itinerary class data for the PPC 440 processor.
102//
103//===----------------------------------------------------------------------===//
104
105
106def PPC440Itineraries : ProcessorItineraries<
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]107 [P440_IFTH1, P440_IFTH2, P440_PDCD1, P440_PDCD2, P440_DISS1, P440_DISS2,
108 P440_FRACC, P440_IRACC, P440_IEXE1, P440_IEXE2, P440_IWB, P440_LRACC,
109 P440_JEXE1, P440_JEXE2, P440_JWB, P440_AGEN, P440_CRD, P440_LWB, P440_FEXE1,
110 P440_FEXE2, P440_FEXE3, P440_FEXE4, P440_FEXE5, P440_FEXE6, P440_FWB,
111 P440_LWARX_Hold],
112 [P440_GPR_Bypass, P440_FPR_Bypass], [
113 InstrItinData<IIC_IntSimple, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
114 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
115 InstrStage<1, [P440_DISS1, P440_DISS2]>,
116 InstrStage<1, [P440_IRACC, P440_LRACC]>,
117 InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
118 InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
119 InstrStage<1, [P440_IWB, P440_JWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]120 [6, 4, 4],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]121 [P440_GPR_Bypass,
122 P440_GPR_Bypass, P440_GPR_Bypass]>,
123 InstrItinData<IIC_IntGeneral, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
124 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
125 InstrStage<1, [P440_DISS1, P440_DISS2]>,
126 InstrStage<1, [P440_IRACC, P440_LRACC]>,
127 InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
128 InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
129 InstrStage<1, [P440_IWB, P440_JWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]130 [6, 4, 4],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]131 [P440_GPR_Bypass,
132 P440_GPR_Bypass, P440_GPR_Bypass]>,
133 InstrItinData<IIC_IntCompare, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
134 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
135 InstrStage<1, [P440_DISS1, P440_DISS2]>,
136 InstrStage<1, [P440_IRACC, P440_LRACC]>,
137 InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
138 InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
139 InstrStage<1, [P440_IWB, P440_JWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]140 [6, 4, 4],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]141 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
142 InstrItinData<IIC_IntDivW, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
143 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
144 InstrStage<1, [P440_DISS1, P440_DISS2]>,
145 InstrStage<1, [P440_IRACC]>,
146 InstrStage<1, [P440_IEXE1]>,
147 InstrStage<1, [P440_IEXE2]>,
148 InstrStage<33, [P440_IWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]149 [40, 4, 4],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]150 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
151 InstrItinData<IIC_IntMFFS, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
152 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
153 InstrStage<1, [P440_DISS1, P440_DISS2]>,
154 InstrStage<1, [P440_IRACC]>,
155 InstrStage<1, [P440_IEXE1]>,
156 InstrStage<1, [P440_IEXE2]>,
157 InstrStage<1, [P440_IWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]158 [7, 4, 4],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]159 [P440_GPR_Bypass,
160 P440_GPR_Bypass, P440_GPR_Bypass]>,
161 InstrItinData<IIC_IntMTFSB0, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
162 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
163 InstrStage<1, [P440_DISS1, P440_DISS2]>,
164 InstrStage<1, [P440_IRACC]>,
165 InstrStage<1, [P440_IEXE1]>,
166 InstrStage<1, [P440_IEXE2]>,
167 InstrStage<1, [P440_IWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]168 [7, 4, 4],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]169 [P440_GPR_Bypass,
170 P440_GPR_Bypass, P440_GPR_Bypass]>,
171 InstrItinData<IIC_IntMulHW, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
172 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
173 InstrStage<1, [P440_DISS1, P440_DISS2]>,
174 InstrStage<1, [P440_IRACC]>,
175 InstrStage<1, [P440_IEXE1]>,
176 InstrStage<1, [P440_IEXE2]>,
177 InstrStage<1, [P440_IWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]178 [8, 4, 4],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]179 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
180 InstrItinData<IIC_IntMulHWU, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
181 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
182 InstrStage<1, [P440_DISS1, P440_DISS2]>,
183 InstrStage<1, [P440_IRACC]>,
184 InstrStage<1, [P440_IEXE1]>,
185 InstrStage<1, [P440_IEXE2]>,
186 InstrStage<1, [P440_IWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]187 [8, 4, 4],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]188 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
189 InstrItinData<IIC_IntMulLI, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
190 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
191 InstrStage<1, [P440_DISS1, P440_DISS2]>,
192 InstrStage<1, [P440_IRACC]>,
193 InstrStage<1, [P440_IEXE1]>,
194 InstrStage<1, [P440_IEXE2]>,
195 InstrStage<1, [P440_IWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]196 [8, 4, 4],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]197 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
198 InstrItinData<IIC_IntRotate, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
199 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
200 InstrStage<1, [P440_DISS1, P440_DISS2]>,
201 InstrStage<1, [P440_IRACC, P440_LRACC]>,
202 InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
203 InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
204 InstrStage<1, [P440_IWB, P440_JWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]205 [6, 4, 4],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]206 [P440_GPR_Bypass,
207 P440_GPR_Bypass, P440_GPR_Bypass]>,
208 InstrItinData<IIC_IntShift, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
209 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
210 InstrStage<1, [P440_DISS1, P440_DISS2]>,
211 InstrStage<1, [P440_IRACC, P440_LRACC]>,
212 InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
213 InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
214 InstrStage<1, [P440_IWB, P440_JWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]215 [6, 4, 4],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]216 [P440_GPR_Bypass,
217 P440_GPR_Bypass, P440_GPR_Bypass]>,
218 InstrItinData<IIC_IntTrapW, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
219 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
220 InstrStage<1, [P440_DISS1, P440_DISS2]>,
221 InstrStage<1, [P440_IRACC]>,
222 InstrStage<1, [P440_IEXE1]>,
223 InstrStage<1, [P440_IEXE2]>,
224 InstrStage<1, [P440_IWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]225 [6, 4],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]226 [P440_GPR_Bypass, P440_GPR_Bypass]>,
227 InstrItinData<IIC_BrB, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
228 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
229 InstrStage<1, [P440_DISS1, P440_DISS2]>,
230 InstrStage<1, [P440_IRACC]>,
231 InstrStage<1, [P440_IEXE1]>,
232 InstrStage<1, [P440_IEXE2]>,
233 InstrStage<1, [P440_IWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]234 [8, 4],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]235 [NoBypass, P440_GPR_Bypass]>,
236 InstrItinData<IIC_BrCR, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
237 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
238 InstrStage<1, [P440_DISS1, P440_DISS2]>,
239 InstrStage<1, [P440_IRACC]>,
240 InstrStage<1, [P440_IEXE1]>,
241 InstrStage<1, [P440_IEXE2]>,
242 InstrStage<1, [P440_IWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]243 [8, 4, 4],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]244 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
245 InstrItinData<IIC_BrMCR, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
246 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
247 InstrStage<1, [P440_DISS1, P440_DISS2]>,
248 InstrStage<1, [P440_IRACC]>,
249 InstrStage<1, [P440_IEXE1]>,
250 InstrStage<1, [P440_IEXE2]>,
251 InstrStage<1, [P440_IWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]252 [8, 4, 4],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]253 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
254 InstrItinData<IIC_BrMCRX, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
255 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
256 InstrStage<1, [P440_DISS1, P440_DISS2]>,
257 InstrStage<1, [P440_IRACC]>,
258 InstrStage<1, [P440_IEXE1]>,
259 InstrStage<1, [P440_IEXE2]>,
260 InstrStage<1, [P440_IWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]261 [8, 4, 4],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]262 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
263 InstrItinData<IIC_LdStDCBA, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
264 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
265 InstrStage<1, [P440_DISS1, P440_DISS2]>,
266 InstrStage<1, [P440_LRACC]>,
267 InstrStage<1, [P440_AGEN]>,
268 InstrStage<1, [P440_CRD]>,
269 InstrStage<1, [P440_LWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]270 [8, 5],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]271 [NoBypass, P440_GPR_Bypass]>,
272 InstrItinData<IIC_LdStDCBF, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
273 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
274 InstrStage<1, [P440_DISS1, P440_DISS2]>,
275 InstrStage<1, [P440_LRACC]>,
276 InstrStage<1, [P440_AGEN]>,
277 InstrStage<1, [P440_CRD]>,
278 InstrStage<1, [P440_LWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]279 [8, 5],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]280 [NoBypass, P440_GPR_Bypass]>,
281 InstrItinData<IIC_LdStDCBI, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
282 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
283 InstrStage<1, [P440_DISS1, P440_DISS2]>,
284 InstrStage<1, [P440_LRACC]>,
285 InstrStage<1, [P440_AGEN]>,
286 InstrStage<1, [P440_CRD]>,
287 InstrStage<1, [P440_LWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]288 [8, 5],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]289 [NoBypass, P440_GPR_Bypass]>,
290 InstrItinData<IIC_LdStLoad, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
291 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
292 InstrStage<1, [P440_DISS1, P440_DISS2]>,
293 InstrStage<1, [P440_LRACC]>,
294 InstrStage<1, [P440_AGEN]>,
295 InstrStage<1, [P440_CRD]>,
296 InstrStage<2, [P440_LWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]297 [9, 5],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]298 [P440_GPR_Bypass, P440_GPR_Bypass]>,
299 InstrItinData<IIC_LdStLoadUpd,[InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
300 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
301 InstrStage<1, [P440_DISS1, P440_DISS2]>,
302 InstrStage<1, [P440_LRACC]>,
303 InstrStage<1, [P440_AGEN]>,
304 InstrStage<1, [P440_CRD]>,
305 InstrStage<2, [P440_LWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]306 [9, 5],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]307 [P440_GPR_Bypass, P440_GPR_Bypass]>,
308 InstrItinData<IIC_LdStStore, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
309 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
310 InstrStage<1, [P440_DISS1, P440_DISS2]>,
311 InstrStage<1, [P440_LRACC]>,
312 InstrStage<1, [P440_AGEN]>,
313 InstrStage<1, [P440_CRD]>,
314 InstrStage<2, [P440_LWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]315 [8, 5],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]316 [NoBypass, P440_GPR_Bypass]>,
317 InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
318 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
319 InstrStage<1, [P440_DISS1, P440_DISS2]>,
320 InstrStage<1, [P440_LRACC]>,
321 InstrStage<1, [P440_AGEN]>,
322 InstrStage<1, [P440_CRD]>,
323 InstrStage<2, [P440_LWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]324 [8, 5],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]325 [NoBypass, P440_GPR_Bypass]>,
326 InstrItinData<IIC_LdStICBI, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
327 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
328 InstrStage<1, [P440_DISS1, P440_DISS2]>,
329 InstrStage<1, [P440_LRACC]>,
330 InstrStage<1, [P440_AGEN]>,
331 InstrStage<1, [P440_CRD]>,
332 InstrStage<1, [P440_LWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]333 [8, 5],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]334 [NoBypass, P440_GPR_Bypass]>,
335 InstrItinData<IIC_LdStSTFD, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
336 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
337 InstrStage<1, [P440_DISS1, P440_DISS2]>,
338 InstrStage<1, [P440_LRACC]>,
339 InstrStage<1, [P440_AGEN]>,
340 InstrStage<1, [P440_CRD]>,
341 InstrStage<1, [P440_LWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]342 [8, 5, 5],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]343 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
344 InstrItinData<IIC_LdStSTFDU, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
345 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
346 InstrStage<1, [P440_DISS1, P440_DISS2]>,
347 InstrStage<1, [P440_LRACC]>,
348 InstrStage<1, [P440_AGEN]>,
349 InstrStage<1, [P440_CRD]>,
350 InstrStage<1, [P440_LWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]351 [8, 5, 5],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]352 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
353 InstrItinData<IIC_LdStLFD, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
354 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
355 InstrStage<1, [P440_DISS1, P440_DISS2]>,
356 InstrStage<1, [P440_LRACC]>,
357 InstrStage<1, [P440_AGEN]>,
358 InstrStage<1, [P440_CRD]>,
359 InstrStage<2, [P440_LWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]360 [9, 5, 5],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]361 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
362 InstrItinData<IIC_LdStLFDU, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
363 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
364 InstrStage<1, [P440_DISS1, P440_DISS2]>,
365 InstrStage<1, [P440_LRACC]>,
366 InstrStage<1, [P440_AGEN]>,
367 InstrStage<1, [P440_CRD]>,
368 InstrStage<1, [P440_LWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]369 [9, 5, 5],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]370 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
371 InstrItinData<IIC_LdStLHA, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
372 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
373 InstrStage<1, [P440_DISS1, P440_DISS2]>,
374 InstrStage<1, [P440_LRACC]>,
375 InstrStage<1, [P440_AGEN]>,
376 InstrStage<1, [P440_CRD]>,
377 InstrStage<1, [P440_LWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]378 [8, 5],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]379 [NoBypass, P440_GPR_Bypass]>,
380 InstrItinData<IIC_LdStLHAU, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
381 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
382 InstrStage<1, [P440_DISS1, P440_DISS2]>,
383 InstrStage<1, [P440_LRACC]>,
384 InstrStage<1, [P440_AGEN]>,
385 InstrStage<1, [P440_CRD]>,
386 InstrStage<1, [P440_LWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]387 [8, 5],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]388 [NoBypass, P440_GPR_Bypass]>,
389 InstrItinData<IIC_LdStLMW, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
390 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
391 InstrStage<1, [P440_DISS1, P440_DISS2]>,
392 InstrStage<1, [P440_LRACC]>,
393 InstrStage<1, [P440_AGEN]>,
394 InstrStage<1, [P440_CRD]>,
395 InstrStage<1, [P440_LWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]396 [8, 5],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]397 [NoBypass, P440_GPR_Bypass]>,
398 InstrItinData<IIC_LdStLWARX, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
399 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
400 InstrStage<1, [P440_DISS1]>,
401 InstrStage<1, [P440_IRACC], 0>,
402 InstrStage<4, [P440_LWARX_Hold], 0>,
403 InstrStage<1, [P440_LRACC]>,
404 InstrStage<1, [P440_AGEN]>,
405 InstrStage<1, [P440_CRD]>,
406 InstrStage<1, [P440_LWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]407 [8, 5],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]408 [NoBypass, P440_GPR_Bypass]>,
409 InstrItinData<IIC_LdStSTD, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
410 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
411 InstrStage<1, [P440_DISS1, P440_DISS2]>,
412 InstrStage<1, [P440_LRACC]>,
413 InstrStage<1, [P440_AGEN]>,
414 InstrStage<1, [P440_CRD]>,
415 InstrStage<2, [P440_LWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]416 [8, 5],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]417 [NoBypass, P440_GPR_Bypass]>,
418 InstrItinData<IIC_LdStSTDU, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
419 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
420 InstrStage<1, [P440_DISS1, P440_DISS2]>,
421 InstrStage<1, [P440_LRACC]>,
422 InstrStage<1, [P440_AGEN]>,
423 InstrStage<1, [P440_CRD]>,
424 InstrStage<2, [P440_LWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]425 [8, 5],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]426 [NoBypass, P440_GPR_Bypass]>,
427 InstrItinData<IIC_LdStSTDCX, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
428 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
429 InstrStage<1, [P440_DISS1]>,
430 InstrStage<1, [P440_IRACC], 0>,
431 InstrStage<4, [P440_LWARX_Hold], 0>,
432 InstrStage<1, [P440_LRACC]>,
433 InstrStage<1, [P440_AGEN]>,
434 InstrStage<1, [P440_CRD]>,
435 InstrStage<1, [P440_LWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]436 [8, 5],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]437 [NoBypass, P440_GPR_Bypass]>,
438 InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
439 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
440 InstrStage<1, [P440_DISS1]>,
441 InstrStage<1, [P440_IRACC], 0>,
442 InstrStage<4, [P440_LWARX_Hold], 0>,
443 InstrStage<1, [P440_LRACC]>,
444 InstrStage<1, [P440_AGEN]>,
445 InstrStage<1, [P440_CRD]>,
446 InstrStage<1, [P440_LWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]447 [8, 5],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]448 [NoBypass, P440_GPR_Bypass]>,
449 InstrItinData<IIC_LdStSync, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
450 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
451 InstrStage<1, [P440_DISS1, P440_DISS2]>,
452 InstrStage<1, [P440_LRACC]>,
453 InstrStage<3, [P440_AGEN], 1>,
454 InstrStage<2, [P440_CRD], 1>,
455 InstrStage<1, [P440_LWB]>]>,
456 InstrItinData<IIC_SprISYNC, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
457 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
458 InstrStage<1, [P440_DISS1, P440_DISS2]>,
459 InstrStage<1, [P440_FRACC], 0>,
460 InstrStage<1, [P440_LRACC], 0>,
461 InstrStage<1, [P440_IRACC]>,
462 InstrStage<1, [P440_FEXE1], 0>,
463 InstrStage<1, [P440_AGEN], 0>,
464 InstrStage<1, [P440_JEXE1], 0>,
465 InstrStage<1, [P440_IEXE1]>,
466 InstrStage<1, [P440_FEXE2], 0>,
467 InstrStage<1, [P440_CRD], 0>,
468 InstrStage<1, [P440_JEXE2], 0>,
469 InstrStage<1, [P440_IEXE2]>,
470 InstrStage<6, [P440_FEXE3], 0>,
471 InstrStage<6, [P440_LWB], 0>,
472 InstrStage<6, [P440_JWB], 0>,
473 InstrStage<6, [P440_IWB]>]>,
474 InstrItinData<IIC_SprMFSR, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
475 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
476 InstrStage<1, [P440_DISS1, P440_DISS2]>,
477 InstrStage<1, [P440_IRACC]>,
478 InstrStage<1, [P440_IEXE1]>,
479 InstrStage<1, [P440_IEXE2]>,
480 InstrStage<1, [P440_IWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]481 [6, 4],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]482 [P440_GPR_Bypass, P440_GPR_Bypass]>,
483 InstrItinData<IIC_SprMTMSR, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
484 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
485 InstrStage<1, [P440_DISS1, P440_DISS2]>,
486 InstrStage<1, [P440_IRACC]>,
487 InstrStage<1, [P440_IEXE1]>,
488 InstrStage<1, [P440_IEXE2]>,
489 InstrStage<1, [P440_IWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]490 [6, 4],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]491 [P440_GPR_Bypass, P440_GPR_Bypass]>,
492 InstrItinData<IIC_SprMTSR, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
493 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
494 InstrStage<1, [P440_DISS1, P440_DISS2]>,
495 InstrStage<1, [P440_IRACC]>,
496 InstrStage<1, [P440_IEXE1]>,
497 InstrStage<1, [P440_IEXE2]>,
498 InstrStage<3, [P440_IWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]499 [9, 4],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]500 [NoBypass, P440_GPR_Bypass]>,
501 InstrItinData<IIC_SprTLBSYNC, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
502 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
503 InstrStage<1, [P440_DISS1, P440_DISS2]>,
504 InstrStage<1, [P440_IRACC]>,
505 InstrStage<1, [P440_IEXE1]>,
506 InstrStage<1, [P440_IEXE2]>,
507 InstrStage<1, [P440_IWB]>]>,
508 InstrItinData<IIC_SprMFCR, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
509 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
510 InstrStage<1, [P440_DISS1, P440_DISS2]>,
511 InstrStage<1, [P440_IRACC]>,
512 InstrStage<1, [P440_IEXE1]>,
513 InstrStage<1, [P440_IEXE2]>,
514 InstrStage<1, [P440_IWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]515 [8, 4],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]516 [NoBypass, P440_GPR_Bypass]>,
517 InstrItinData<IIC_SprMFMSR, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
518 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
519 InstrStage<1, [P440_DISS1, P440_DISS2]>,
520 InstrStage<1, [P440_IRACC]>,
521 InstrStage<1, [P440_IEXE1]>,
522 InstrStage<1, [P440_IEXE2]>,
523 InstrStage<1, [P440_IWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]524 [7, 4],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]525 [P440_GPR_Bypass, P440_GPR_Bypass]>,
526 InstrItinData<IIC_SprMFSPR, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
527 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
528 InstrStage<1, [P440_DISS1, P440_DISS2]>,
529 InstrStage<1, [P440_IRACC]>,
530 InstrStage<1, [P440_IEXE1]>,
531 InstrStage<1, [P440_IEXE2]>,
532 InstrStage<3, [P440_IWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]533 [10, 4],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]534 [NoBypass, P440_GPR_Bypass]>,
535 InstrItinData<IIC_SprMFTB, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
536 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
537 InstrStage<1, [P440_DISS1, P440_DISS2]>,
538 InstrStage<1, [P440_IRACC]>,
539 InstrStage<1, [P440_IEXE1]>,
540 InstrStage<1, [P440_IEXE2]>,
541 InstrStage<3, [P440_IWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]542 [10, 4],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]543 [NoBypass, P440_GPR_Bypass]>,
544 InstrItinData<IIC_SprMTSPR, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
545 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
546 InstrStage<1, [P440_DISS1, P440_DISS2]>,
547 InstrStage<1, [P440_IRACC]>,
548 InstrStage<1, [P440_IEXE1]>,
549 InstrStage<1, [P440_IEXE2]>,
550 InstrStage<3, [P440_IWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]551 [10, 4],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]552 [NoBypass, P440_GPR_Bypass]>,
553 InstrItinData<IIC_SprMTSRIN, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
554 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
555 InstrStage<1, [P440_DISS1, P440_DISS2]>,
556 InstrStage<1, [P440_IRACC]>,
557 InstrStage<1, [P440_IEXE1]>,
558 InstrStage<1, [P440_IEXE2]>,
559 InstrStage<3, [P440_IWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]560 [10, 4],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]561 [NoBypass, P440_GPR_Bypass]>,
562 InstrItinData<IIC_SprRFI, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
563 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
564 InstrStage<1, [P440_DISS1, P440_DISS2]>,
565 InstrStage<1, [P440_IRACC]>,
566 InstrStage<1, [P440_IEXE1]>,
567 InstrStage<1, [P440_IEXE2]>,
568 InstrStage<1, [P440_IWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]569 [8, 4],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]570 [NoBypass, P440_GPR_Bypass]>,
571 InstrItinData<IIC_SprSC, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
572 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
573 InstrStage<1, [P440_DISS1, P440_DISS2]>,
574 InstrStage<1, [P440_IRACC]>,
575 InstrStage<1, [P440_IEXE1]>,
576 InstrStage<1, [P440_IEXE2]>,
577 InstrStage<1, [P440_IWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]578 [8, 4],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]579 [NoBypass, P440_GPR_Bypass]>,
580 InstrItinData<IIC_FPGeneral, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
581 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
582 InstrStage<1, [P440_DISS1, P440_DISS2]>,
583 InstrStage<1, [P440_FRACC]>,
584 InstrStage<1, [P440_FEXE1]>,
585 InstrStage<1, [P440_FEXE2]>,
586 InstrStage<1, [P440_FEXE3]>,
587 InstrStage<1, [P440_FEXE4]>,
588 InstrStage<1, [P440_FEXE5]>,
589 InstrStage<1, [P440_FEXE6]>,
590 InstrStage<1, [P440_FWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]591 [10, 4, 4],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]592 [P440_FPR_Bypass,
593 P440_FPR_Bypass, P440_FPR_Bypass]>,
594 InstrItinData<IIC_FPAddSub, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
595 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
596 InstrStage<1, [P440_DISS1, P440_DISS2]>,
597 InstrStage<1, [P440_FRACC]>,
598 InstrStage<1, [P440_FEXE1]>,
599 InstrStage<1, [P440_FEXE2]>,
600 InstrStage<1, [P440_FEXE3]>,
601 InstrStage<1, [P440_FEXE4]>,
602 InstrStage<1, [P440_FEXE5]>,
603 InstrStage<1, [P440_FEXE6]>,
604 InstrStage<1, [P440_FWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]605 [10, 4, 4],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]606 [P440_FPR_Bypass,
607 P440_FPR_Bypass, P440_FPR_Bypass]>,
608 InstrItinData<IIC_FPCompare, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
609 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
610 InstrStage<1, [P440_DISS1, P440_DISS2]>,
611 InstrStage<1, [P440_FRACC]>,
612 InstrStage<1, [P440_FEXE1]>,
613 InstrStage<1, [P440_FEXE2]>,
614 InstrStage<1, [P440_FEXE3]>,
615 InstrStage<1, [P440_FEXE4]>,
616 InstrStage<1, [P440_FEXE5]>,
617 InstrStage<1, [P440_FEXE6]>,
618 InstrStage<1, [P440_FWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]619 [10, 4, 4],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]620 [P440_FPR_Bypass, P440_FPR_Bypass,
621 P440_FPR_Bypass]>,
622 InstrItinData<IIC_FPDivD, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
623 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
624 InstrStage<1, [P440_DISS1, P440_DISS2]>,
625 InstrStage<1, [P440_FRACC]>,
626 InstrStage<1, [P440_FEXE1]>,
627 InstrStage<1, [P440_FEXE2]>,
628 InstrStage<1, [P440_FEXE3]>,
629 InstrStage<1, [P440_FEXE4]>,
630 InstrStage<1, [P440_FEXE5]>,
631 InstrStage<1, [P440_FEXE6]>,
632 InstrStage<25, [P440_FWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]633 [35, 4, 4],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]634 [NoBypass, P440_FPR_Bypass, P440_FPR_Bypass]>,
635 InstrItinData<IIC_FPDivS, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
636 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
637 InstrStage<1, [P440_DISS1, P440_DISS2]>,
638 InstrStage<1, [P440_FRACC]>,
639 InstrStage<1, [P440_FEXE1]>,
640 InstrStage<1, [P440_FEXE2]>,
641 InstrStage<1, [P440_FEXE3]>,
642 InstrStage<1, [P440_FEXE4]>,
643 InstrStage<1, [P440_FEXE5]>,
644 InstrStage<1, [P440_FEXE6]>,
645 InstrStage<13, [P440_FWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]646 [23, 4, 4],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]647 [NoBypass, P440_FPR_Bypass, P440_FPR_Bypass]>,
648 InstrItinData<IIC_FPFused, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
649 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
650 InstrStage<1, [P440_DISS1, P440_DISS2]>,
651 InstrStage<1, [P440_FRACC]>,
652 InstrStage<1, [P440_FEXE1]>,
653 InstrStage<1, [P440_FEXE2]>,
654 InstrStage<1, [P440_FEXE3]>,
655 InstrStage<1, [P440_FEXE4]>,
656 InstrStage<1, [P440_FEXE5]>,
657 InstrStage<1, [P440_FEXE6]>,
658 InstrStage<1, [P440_FWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]659 [10, 4, 4, 4],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]660 [P440_FPR_Bypass,
661 P440_FPR_Bypass, P440_FPR_Bypass,
662 P440_FPR_Bypass]>,
663 InstrItinData<IIC_FPRes, [InstrStage<1, [P440_IFTH1, P440_IFTH2]>,
664 InstrStage<1, [P440_PDCD1, P440_PDCD2]>,
665 InstrStage<1, [P440_DISS1, P440_DISS2]>,
666 InstrStage<1, [P440_FRACC]>,
667 InstrStage<1, [P440_FEXE1]>,
668 InstrStage<1, [P440_FEXE2]>,
669 InstrStage<1, [P440_FEXE3]>,
670 InstrStage<1, [P440_FEXE4]>,
671 InstrStage<1, [P440_FEXE5]>,
672 InstrStage<1, [P440_FEXE6]>,
673 InstrStage<1, [P440_FWB]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]674 [10, 4],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]675 [P440_FPR_Bypass, P440_FPR_Bypass]>
Hal Finkelad677b62011-10-17 04:03:55 +0000[diff] [blame]676]>;