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gerrit-public.fairphone.software / toolchain / llvm-project / 92720ab1b2b3b0769ba99d5f0169e927ac0bd4e2 / . / llvm / lib / Target / PowerPC / PPCScheduleE500mc.td
blob: 906c685d54650b3e1b183748bf2fe4a522a59856 [file] [log] [blame]
Hal Finkel742b5352012-08-28 16:12:39 +0000[diff] [blame]1//===-- PPCScheduleE500mc.td - e500mc Scheduling Defs ------*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the itinerary class data for the Freescale e500mc 32-bit
11// Power processor.
12//
13// All information is derived from the "e500mc Core Reference Manual",
14// Freescale Document Number E500MCRM, Rev. 1, 03/2012.
15//
16//===----------------------------------------------------------------------===//
17// Relevant functional units in the Freescale e500mc core:
18//
19// * Decode & Dispatch
20// Can dispatch up to 2 instructions per clock cycle to either the GPR Issue
21// queues (GIQx), FP Issue Queue (FIQ), or Branch issue queue (BIQ).
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]22def E500_DIS0 : FuncUnit; // Dispatch stage - insn 1
23def E500_DIS1 : FuncUnit; // Dispatch stage - insn 2
Hal Finkel742b5352012-08-28 16:12:39 +0000[diff] [blame]24
25// * Execute
26// 6 pipelined execution units: SFX0, SFX1, BU, FPU, LSU, CFX.
27// Some instructions can only execute in SFX0 but not SFX1.
28// The CFX has a bypass path, allowing non-divide instructions to execute
29// while a divide instruction is executed.
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]30def E500_SFX0 : FuncUnit; // Simple unit 0
31def E500_SFX1 : FuncUnit; // Simple unit 1
32def E500_BU : FuncUnit; // Branch unit
33def E500_CFX_DivBypass
34 : FuncUnit; // CFX divide bypass path
35def E500_CFX_0 : FuncUnit; // CFX pipeline
36def E500_LSU_0 : FuncUnit; // LSU pipeline
37def E500_FPU_0 : FuncUnit; // FPU pipeline
Hal Finkel742b5352012-08-28 16:12:39 +0000[diff] [blame]38
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]39def E500_GPR_Bypass : Bypass;
40def E500_FPR_Bypass : Bypass;
41def E500_CR_Bypass : Bypass;
Hal Finkelf574c272013-09-11 23:25:21 +0000[diff] [blame]42
Hal Finkel742b5352012-08-28 16:12:39 +0000[diff] [blame]43def PPCE500mcItineraries : ProcessorItineraries<
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]44 [E500_DIS0, E500_DIS1, E500_SFX0, E500_SFX1, E500_BU, E500_CFX_DivBypass,
45 E500_CFX_0, E500_LSU_0, E500_FPU_0],
46 [E500_CR_Bypass, E500_GPR_Bypass, E500_FPR_Bypass], [
47 InstrItinData<IIC_IntSimple, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
48 InstrStage<1, [E500_SFX0, E500_SFX1]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]49 [4, 1, 1], // Latency = 1
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]50 [E500_GPR_Bypass,
51 E500_GPR_Bypass, E500_GPR_Bypass]>,
52 InstrItinData<IIC_IntGeneral, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
53 InstrStage<1, [E500_SFX0, E500_SFX1]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]54 [4, 1, 1], // Latency = 1
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]55 [E500_GPR_Bypass,
56 E500_GPR_Bypass, E500_GPR_Bypass]>,
57 InstrItinData<IIC_IntCompare, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
58 InstrStage<1, [E500_SFX0, E500_SFX1]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]59 [5, 1, 1], // Latency = 1 or 2
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]60 [E500_CR_Bypass,
61 E500_GPR_Bypass, E500_GPR_Bypass]>,
62 InstrItinData<IIC_IntDivW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
63 InstrStage<1, [E500_CFX_0], 0>,
64 InstrStage<14, [E500_CFX_DivBypass]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]65 [17, 1, 1], // Latency=4..35, Repeat= 4..35
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]66 [E500_GPR_Bypass,
67 E500_GPR_Bypass, E500_GPR_Bypass]>,
68 InstrItinData<IIC_IntMFFS, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
69 InstrStage<8, [E500_FPU_0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]70 [11], // Latency = 8
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]71 [E500_FPR_Bypass]>,
72 InstrItinData<IIC_IntMTFSB0, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
73 InstrStage<8, [E500_FPU_0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]74 [11, 1, 1], // Latency = 8
75 [NoBypass, NoBypass, NoBypass]>,
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]76 InstrItinData<IIC_IntMulHW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
77 InstrStage<1, [E500_CFX_0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]78 [7, 1, 1], // Latency = 4, Repeat rate = 1
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]79 [E500_GPR_Bypass,
80 E500_GPR_Bypass, E500_GPR_Bypass]>,
81 InstrItinData<IIC_IntMulHWU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
82 InstrStage<1, [E500_CFX_0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]83 [7, 1, 1], // Latency = 4, Repeat rate = 1
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]84 [E500_GPR_Bypass,
85 E500_GPR_Bypass, E500_GPR_Bypass]>,
86 InstrItinData<IIC_IntMulLI, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
87 InstrStage<1, [E500_CFX_0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]88 [7, 1, 1], // Latency = 4, Repeat rate = 1
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]89 [E500_GPR_Bypass,
90 E500_GPR_Bypass, E500_GPR_Bypass]>,
91 InstrItinData<IIC_IntRotate, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
92 InstrStage<1, [E500_SFX0, E500_SFX1]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]93 [4, 1, 1], // Latency = 1
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]94 [E500_GPR_Bypass,
95 E500_GPR_Bypass, E500_GPR_Bypass]>,
96 InstrItinData<IIC_IntShift, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
97 InstrStage<1, [E500_SFX0, E500_SFX1]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]98 [4, 1, 1], // Latency = 1
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]99 [E500_GPR_Bypass,
100 E500_GPR_Bypass, E500_GPR_Bypass]>,
101 InstrItinData<IIC_IntTrapW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
102 InstrStage<2, [E500_SFX0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]103 [5, 1], // Latency = 2, Repeat rate = 2
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]104 [E500_GPR_Bypass, E500_GPR_Bypass]>,
105 InstrItinData<IIC_BrB, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
106 InstrStage<1, [E500_BU]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]107 [4, 1], // Latency = 1
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]108 [NoBypass, E500_GPR_Bypass]>,
109 InstrItinData<IIC_BrCR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
110 InstrStage<1, [E500_BU]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]111 [4, 1, 1], // Latency = 1
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]112 [E500_CR_Bypass,
113 E500_CR_Bypass, E500_CR_Bypass]>,
114 InstrItinData<IIC_BrMCR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
115 InstrStage<1, [E500_BU]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]116 [4, 1], // Latency = 1
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]117 [E500_CR_Bypass, E500_CR_Bypass]>,
118 InstrItinData<IIC_BrMCRX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
119 InstrStage<1, [E500_SFX0, E500_SFX1]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]120 [4, 1, 1], // Latency = 1
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]121 [E500_CR_Bypass, E500_GPR_Bypass]>,
122 InstrItinData<IIC_LdStDCBA, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
123 InstrStage<1, [E500_LSU_0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]124 [6, 1], // Latency = 3, Repeat rate = 1
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]125 [E500_GPR_Bypass, E500_GPR_Bypass]>,
126 InstrItinData<IIC_LdStDCBF, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
127 InstrStage<1, [E500_LSU_0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]128 [6, 1], // Latency = 3
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]129 [E500_GPR_Bypass, E500_GPR_Bypass]>,
130 InstrItinData<IIC_LdStDCBI, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
131 InstrStage<1, [E500_LSU_0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]132 [6, 1], // Latency = 3
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]133 [E500_GPR_Bypass, E500_GPR_Bypass]>,
134 InstrItinData<IIC_LdStLoad, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
135 InstrStage<1, [E500_LSU_0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]136 [6, 1], // Latency = 3
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]137 [E500_GPR_Bypass, E500_GPR_Bypass]>,
138 InstrItinData<IIC_LdStLoadUpd, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
139 InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
140 InstrStage<1, [E500_LSU_0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]141 [6, 1], // Latency = 3
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]142 [E500_GPR_Bypass, E500_GPR_Bypass],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]143 2>, // 2 micro-ops
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]144 InstrItinData<IIC_LdStStore, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
145 InstrStage<1, [E500_LSU_0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]146 [6, 1], // Latency = 3
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]147 [NoBypass, E500_GPR_Bypass]>,
148 InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
149 InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
150 InstrStage<1, [E500_LSU_0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]151 [6, 1], // Latency = 3
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]152 [NoBypass, E500_GPR_Bypass],
153 2>, // 2 micro-ops
154 InstrItinData<IIC_LdStICBI, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
155 InstrStage<1, [E500_LSU_0]>],
156 [6, 1], // Latency = 3
157 [NoBypass, E500_GPR_Bypass]>,
158 InstrItinData<IIC_LdStSTFD, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
159 InstrStage<1, [E500_LSU_0]>],
160 [6, 1, 1], // Latency = 3
161 [E500_GPR_Bypass,
162 E500_GPR_Bypass, E500_GPR_Bypass]>,
163 InstrItinData<IIC_LdStSTFDU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
164 InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
165 InstrStage<1, [E500_LSU_0]>],
166 [6, 1, 1], // Latency = 3
167 [E500_GPR_Bypass,
168 E500_GPR_Bypass, E500_GPR_Bypass],
169 2>, // 2 micro-ops
170 InstrItinData<IIC_LdStLFD, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
171 InstrStage<1, [E500_LSU_0]>],
172 [7, 1, 1], // Latency = 4
173 [E500_FPR_Bypass,
174 E500_GPR_Bypass, E500_GPR_Bypass]>,
175 InstrItinData<IIC_LdStLFDU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
176 InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
177 InstrStage<1, [E500_LSU_0]>],
178 [7, 1, 1], // Latency = 4
179 [E500_FPR_Bypass,
180 E500_GPR_Bypass, E500_GPR_Bypass],
181 2>, // 2 micro-ops
182 InstrItinData<IIC_LdStLHA, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
183 InstrStage<1, [E500_LSU_0]>],
184 [6, 1], // Latency = 3
185 [E500_GPR_Bypass, E500_GPR_Bypass]>,
186 InstrItinData<IIC_LdStLHAU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
187 InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
188 InstrStage<1, [E500_LSU_0]>],
189 [6, 1], // Latency = 3
190 [E500_GPR_Bypass, E500_GPR_Bypass]>,
191 InstrItinData<IIC_LdStLMW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
192 InstrStage<1, [E500_LSU_0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]193 [7, 1], // Latency = r+3
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]194 [NoBypass, E500_GPR_Bypass]>,
195 InstrItinData<IIC_LdStLWARX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
196 InstrStage<3, [E500_LSU_0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]197 [6, 1, 1], // Latency = 3, Repeat rate = 3
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]198 [E500_GPR_Bypass,
199 E500_GPR_Bypass, E500_GPR_Bypass]>,
200 InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
201 InstrStage<1, [E500_LSU_0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]202 [6, 1], // Latency = 3
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]203 [NoBypass, E500_GPR_Bypass]>,
204 InstrItinData<IIC_LdStSync, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
205 InstrStage<1, [E500_LSU_0]>]>,
206 InstrItinData<IIC_SprMFSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
207 InstrStage<4, [E500_SFX0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]208 [7, 1],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]209 [E500_GPR_Bypass, E500_GPR_Bypass]>,
210 InstrItinData<IIC_SprMTMSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
211 InstrStage<2, [E500_SFX0, E500_SFX1]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]212 [5, 1], // Latency = 2, Repeat rate = 4
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]213 [E500_GPR_Bypass, E500_GPR_Bypass]>,
214 InstrItinData<IIC_SprMTSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
215 InstrStage<1, [E500_SFX0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]216 [5, 1],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]217 [NoBypass, E500_GPR_Bypass]>,
218 InstrItinData<IIC_SprTLBSYNC, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
219 InstrStage<1, [E500_LSU_0], 0>]>,
220 InstrItinData<IIC_SprMFCR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
221 InstrStage<5, [E500_SFX0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]222 [8, 1],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]223 [E500_GPR_Bypass, E500_CR_Bypass]>,
224 InstrItinData<IIC_SprMFMSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
225 InstrStage<4, [E500_SFX0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]226 [7, 1], // Latency = 4, Repeat rate = 4
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]227 [E500_GPR_Bypass, E500_GPR_Bypass]>,
228 InstrItinData<IIC_SprMFSPR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
229 InstrStage<1, [E500_SFX0, E500_SFX1]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]230 [4, 1], // Latency = 1, Repeat rate = 1
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]231 [E500_GPR_Bypass, E500_CR_Bypass]>,
232 InstrItinData<IIC_SprMFTB, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
233 InstrStage<4, [E500_SFX0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]234 [7, 1], // Latency = 4, Repeat rate = 4
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]235 [NoBypass, E500_GPR_Bypass]>,
236 InstrItinData<IIC_SprMTSPR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
237 InstrStage<1, [E500_SFX0, E500_SFX1]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]238 [4, 1], // Latency = 1, Repeat rate = 1
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]239 [E500_CR_Bypass, E500_GPR_Bypass]>,
240 InstrItinData<IIC_SprMTSRIN, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
241 InstrStage<1, [E500_SFX0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]242 [4, 1],
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]243 [NoBypass, E500_GPR_Bypass]>,
244 InstrItinData<IIC_FPGeneral, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
245 InstrStage<2, [E500_FPU_0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]246 [11, 1, 1], // Latency = 8, Repeat rate = 2
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]247 [E500_FPR_Bypass,
248 E500_FPR_Bypass, E500_FPR_Bypass]>,
249 InstrItinData<IIC_FPAddSub, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
250 InstrStage<4, [E500_FPU_0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]251 [13, 1, 1], // Latency = 10, Repeat rate = 4
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]252 [E500_FPR_Bypass,
253 E500_FPR_Bypass, E500_FPR_Bypass]>,
254 InstrItinData<IIC_FPCompare, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
255 InstrStage<2, [E500_FPU_0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]256 [11, 1, 1], // Latency = 8, Repeat rate = 2
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]257 [E500_CR_Bypass,
258 E500_FPR_Bypass, E500_FPR_Bypass]>,
259 InstrItinData<IIC_FPDivD, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
260 InstrStage<68, [E500_FPU_0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]261 [71, 1, 1], // Latency = 68, Repeat rate = 68
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]262 [E500_FPR_Bypass,
263 E500_FPR_Bypass, E500_FPR_Bypass]>,
264 InstrItinData<IIC_FPDivS, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
265 InstrStage<38, [E500_FPU_0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]266 [41, 1, 1], // Latency = 38, Repeat rate = 38
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]267 [E500_FPR_Bypass,
268 E500_FPR_Bypass, E500_FPR_Bypass]>,
269 InstrItinData<IIC_FPFused, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
270 InstrStage<4, [E500_FPU_0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]271 [13, 1, 1, 1], // Latency = 10, Repeat rate = 4
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]272 [E500_FPR_Bypass,
273 E500_FPR_Bypass, E500_FPR_Bypass,
274 E500_FPR_Bypass]>,
275 InstrItinData<IIC_FPRes, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
276 InstrStage<38, [E500_FPU_0]>],
Hal Finkel3e5a3602013-11-27 23:26:09 +0000[diff] [blame]277 [41, 1], // Latency = 38, Repeat rate = 38
Hal Finkel92720ab2013-11-28 06:05:59 +0000[diff] [blame^]278 [E500_FPR_Bypass, E500_FPR_Bypass]>
Hal Finkel742b5352012-08-28 16:12:39 +0000[diff] [blame]279]>;
280
281// ===---------------------------------------------------------------------===//
282// e500mc machine model for scheduling and other instruction cost heuristics.
283
284def PPCE500mcModel : SchedMachineModel {
285 let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.
286 let MinLatency = -1; // OperandCycles are interpreted as MinLatency.
287 let LoadLatency = 5; // Optimistic load latency assuming bypass.
288 // This is overriden by OperandCycles if the
289 // Itineraries are queried instead.
290
291 let Itineraries = PPCE500mcItineraries;
292}