Clement Courbet | d939f6d | 2018-09-13 07:40:53 +0000 | [diff] [blame] | 1 | //===-- SnippetGenerator.cpp ------------------------------------*- C++ -*-===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | |
| 10 | #include <array> |
| 11 | #include <string> |
| 12 | |
| 13 | #include "Assembler.h" |
| 14 | #include "MCInstrDescView.h" |
| 15 | #include "SnippetGenerator.h" |
| 16 | #include "llvm/ADT/StringExtras.h" |
| 17 | #include "llvm/ADT/StringRef.h" |
| 18 | #include "llvm/ADT/Twine.h" |
| 19 | #include "llvm/Support/FileSystem.h" |
| 20 | #include "llvm/Support/FormatVariadic.h" |
| 21 | #include "llvm/Support/Program.h" |
| 22 | |
| 23 | namespace exegesis { |
| 24 | |
| 25 | SnippetGeneratorFailure::SnippetGeneratorFailure(const llvm::Twine &S) |
| 26 | : llvm::StringError(S, llvm::inconvertibleErrorCode()) {} |
| 27 | |
| 28 | SnippetGenerator::SnippetGenerator(const LLVMState &State) |
| 29 | : State(State), RATC(State.getRegInfo(), |
| 30 | getFunctionReservedRegs(State.getTargetMachine())) {} |
| 31 | |
| 32 | SnippetGenerator::~SnippetGenerator() = default; |
| 33 | |
| 34 | llvm::Expected<std::vector<BenchmarkCode>> |
| 35 | SnippetGenerator::generateConfigurations(unsigned Opcode) const { |
| 36 | if (auto E = generateCodeTemplate(Opcode)) { |
| 37 | CodeTemplate &CT = E.get(); |
| 38 | std::vector<BenchmarkCode> Output; |
| 39 | // TODO: Generate as many BenchmarkCode as needed. |
| 40 | { |
| 41 | BenchmarkCode BC; |
| 42 | BC.Info = CT.Info; |
| 43 | for (InstructionBuilder &IB : CT.Instructions) { |
| 44 | IB.randomizeUnsetVariables( |
| 45 | CT.ScratchSpacePointerInReg |
| 46 | ? RATC.getRegister(CT.ScratchSpacePointerInReg).aliasedBits() |
| 47 | : RATC.emptyRegisters()); |
| 48 | BC.Instructions.push_back(IB.build()); |
| 49 | } |
| 50 | if (CT.ScratchSpacePointerInReg) |
| 51 | BC.LiveIns.push_back(CT.ScratchSpacePointerInReg); |
Guillaume Chatelet | 937f3fe | 2018-09-18 11:26:48 +0000 | [diff] [blame^] | 52 | BC.RegisterInitialValues = computeRegisterInitialValues(CT.Instructions); |
Clement Courbet | d939f6d | 2018-09-13 07:40:53 +0000 | [diff] [blame] | 53 | Output.push_back(std::move(BC)); |
| 54 | } |
| 55 | return Output; |
| 56 | } else |
| 57 | return E.takeError(); |
| 58 | } |
| 59 | |
Guillaume Chatelet | 937f3fe | 2018-09-18 11:26:48 +0000 | [diff] [blame^] | 60 | std::vector<RegisterValue> SnippetGenerator::computeRegisterInitialValues( |
Clement Courbet | d939f6d | 2018-09-13 07:40:53 +0000 | [diff] [blame] | 61 | const std::vector<InstructionBuilder> &Instructions) const { |
| 62 | // Collect all register uses and create an assignment for each of them. |
| 63 | // Ignore memory operands which are handled separately. |
| 64 | // Loop invariant: DefinedRegs[i] is true iif it has been set at least once |
| 65 | // before the current instruction. |
| 66 | llvm::BitVector DefinedRegs = RATC.emptyRegisters(); |
Guillaume Chatelet | 937f3fe | 2018-09-18 11:26:48 +0000 | [diff] [blame^] | 67 | std::vector<RegisterValue> RIV; |
Clement Courbet | d939f6d | 2018-09-13 07:40:53 +0000 | [diff] [blame] | 68 | for (const InstructionBuilder &IB : Instructions) { |
| 69 | // Returns the register that this Operand sets or uses, or 0 if this is not |
| 70 | // a register. |
| 71 | const auto GetOpReg = [&IB](const Operand &Op) -> unsigned { |
| 72 | if (Op.IsMem) |
| 73 | return 0; |
| 74 | if (Op.ImplicitReg) |
| 75 | return *Op.ImplicitReg; |
| 76 | if (Op.IsExplicit && IB.getValueFor(Op).isReg()) |
| 77 | return IB.getValueFor(Op).getReg(); |
| 78 | return 0; |
| 79 | }; |
| 80 | // Collect used registers that have never been def'ed. |
| 81 | for (const Operand &Op : IB.Instr.Operands) { |
| 82 | if (!Op.IsDef) { |
| 83 | const unsigned Reg = GetOpReg(Op); |
| 84 | if (Reg > 0 && !DefinedRegs.test(Reg)) { |
Guillaume Chatelet | 937f3fe | 2018-09-18 11:26:48 +0000 | [diff] [blame^] | 85 | RIV.push_back(RegisterValue{Reg, llvm::APInt()}); |
Clement Courbet | d939f6d | 2018-09-13 07:40:53 +0000 | [diff] [blame] | 86 | DefinedRegs.set(Reg); |
| 87 | } |
| 88 | } |
| 89 | } |
| 90 | // Mark defs as having been def'ed. |
| 91 | for (const Operand &Op : IB.Instr.Operands) { |
| 92 | if (Op.IsDef) { |
| 93 | const unsigned Reg = GetOpReg(Op); |
| 94 | if (Reg > 0) |
| 95 | DefinedRegs.set(Reg); |
| 96 | } |
| 97 | } |
| 98 | } |
Guillaume Chatelet | 937f3fe | 2018-09-18 11:26:48 +0000 | [diff] [blame^] | 99 | return RIV; |
Clement Courbet | d939f6d | 2018-09-13 07:40:53 +0000 | [diff] [blame] | 100 | } |
| 101 | |
| 102 | llvm::Expected<CodeTemplate> SnippetGenerator::generateSelfAliasingCodeTemplate( |
| 103 | const Instruction &Instr) const { |
| 104 | const AliasingConfigurations SelfAliasing(Instr, Instr); |
| 105 | if (SelfAliasing.empty()) { |
| 106 | return llvm::make_error<SnippetGeneratorFailure>("empty self aliasing"); |
| 107 | } |
| 108 | CodeTemplate CT; |
| 109 | InstructionBuilder IB(Instr); |
| 110 | if (SelfAliasing.hasImplicitAliasing()) { |
| 111 | CT.Info = "implicit Self cycles, picking random values."; |
| 112 | } else { |
| 113 | CT.Info = "explicit self cycles, selecting one aliasing Conf."; |
| 114 | // This is a self aliasing instruction so defs and uses are from the same |
| 115 | // instance, hence twice IB in the following call. |
| 116 | setRandomAliasing(SelfAliasing, IB, IB); |
| 117 | } |
| 118 | CT.Instructions.push_back(std::move(IB)); |
| 119 | return std::move(CT); |
| 120 | } |
| 121 | |
| 122 | llvm::Expected<CodeTemplate> |
| 123 | SnippetGenerator::generateUnconstrainedCodeTemplate(const Instruction &Instr, |
| 124 | llvm::StringRef Msg) const { |
| 125 | CodeTemplate CT; |
| 126 | CT.Info = llvm::formatv("{0}, repeating an unconstrained assignment", Msg); |
| 127 | CT.Instructions.emplace_back(Instr); |
| 128 | return std::move(CT); |
| 129 | } |
| 130 | } // namespace exegesis |