Gitiles
Code Review Sign In
gerrit-public.fairphone.software / toolchain / llvm-project / 9969d3e6e86236878fd4b4fab55473870290d709 / . / llvm / test / CodeGen / X86 / anyregcc.ll
blob: 710b6a088fa2b1e6d091300e23ccbab4382b3978 [file] [log] [blame]
Juergen Ributzka9969d3e2013-11-08 23:28:16 +0000[diff] [blame^]1; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
2
3; Stackmap Header: no constants - 6 callsites
4; CHECK-LABEL: .section __LLVM_STACKMAPS,__llvm_stackmaps
5; CHECK-NEXT: __LLVM_StackMaps:
6; Header
7; CHECK-NEXT: .long 0
8; Num Constants
9; CHECK-NEXT: .long 0
10; Num Callsites
11; CHECK-NEXT: .long 6
12
13; test
14; CHECK-NEXT: .long 0
15; CHECK-NEXT: .long L{{.*}}-_test
16; CHECK-NEXT: .short 0
17; 3 locations
18; CHECK-NEXT: .short 3
19; Loc 0: Register
20; CHECK-NEXT: .byte 1
21; CHECK-NEXT: .byte 0
22; CHECK-NEXT: .short {{[0-9]+}}
23; CHECK-NEXT: .long 0
24; Loc 1: Register
25; CHECK-NEXT: .byte 1
26; CHECK-NEXT: .byte 0
27; CHECK-NEXT: .short {{[0-9]+}}
28; CHECK-NEXT: .long 0
29; Loc 2: Constant 3
30; CHECK-NEXT: .byte 4
31; CHECK-NEXT: .byte 0
32; CHECK-NEXT: .short 0
33; CHECK-NEXT: .long 3
34define i64 @test() nounwind ssp uwtable {
35entry:
36 call anyregcc void (i32, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i32 0, i32 12, i8* null, i32 2, i32 1, i32 2, i64 3)
37 ret i64 0
38}
39
40; property access 1 - %obj is an anyreg call argument and should therefore be in a register
41; CHECK-NEXT: .long 1
42; CHECK-NEXT: .long L{{.*}}-_property_access1
43; CHECK-NEXT: .short 0
44; 2 locations
45; CHECK-NEXT: .short 2
46; Loc 0: Register <-- this is the return register
47; CHECK-NEXT: .byte 1
48; CHECK-NEXT: .byte 0
49; CHECK-NEXT: .short {{[0-9]+}}
50; CHECK-NEXT: .long 0
51; Loc 1: Register
52; CHECK-NEXT: .byte 1
53; CHECK-NEXT: .byte 0
54; CHECK-NEXT: .short {{[0-9]+}}
55; CHECK-NEXT: .long 0
56define i64 @property_access1(i8* %obj) nounwind ssp uwtable {
57entry:
58 %f = inttoptr i64 12297829382473034410 to i8*
59 %ret = call anyregcc i64 (i32, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i32 1, i32 12, i8* %f, i32 1, i8* %obj)
60 ret i64 %ret
61}
62
63; property access 2 - %obj is an anyreg call argument and should therefore be in a register
64; CHECK-NEXT: .long 2
65; CHECK-NEXT: .long L{{.*}}-_property_access2
66; CHECK-NEXT: .short 0
67; 2 locations
68; CHECK-NEXT: .short 2
69; Loc 0: Register <-- this is the return register
70; CHECK-NEXT: .byte 1
71; CHECK-NEXT: .byte 0
72; CHECK-NEXT: .short {{[0-9]+}}
73; CHECK-NEXT: .long 0
74; Loc 1: Register
75; CHECK-NEXT: .byte 1
76; CHECK-NEXT: .byte 0
77; CHECK-NEXT: .short {{[0-9]+}}
78; CHECK-NEXT: .long 0
79define i64 @property_access2() nounwind ssp uwtable {
80entry:
81 %obj = alloca i64, align 8
82 %f = inttoptr i64 12297829382473034410 to i8*
83 %ret = call anyregcc i64 (i32, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i32 2, i32 12, i8* %f, i32 1, i64* %obj)
84 ret i64 %ret
85}
86
87; property access 3 - %obj is a frame index
88; CHECK-NEXT: .long 3
89; CHECK-NEXT: .long L{{.*}}-_property_access3
90; CHECK-NEXT: .short 0
91; 2 locations
92; CHECK-NEXT: .short 2
93; Loc 0: Register <-- this is the return register
94; CHECK-NEXT: .byte 1
95; CHECK-NEXT: .byte 0
96; CHECK-NEXT: .short {{[0-9]+}}
97; CHECK-NEXT: .long 0
98; Loc 1: Register <-- this will be folded once folding for FI is implemented
99; CHECK-NEXT: .byte 1
100; CHECK-NEXT: .byte 0
101; CHECK-NEXT: .short {{[0-9]+}}
102; CHECK-NEXT: .long 0
103define i64 @property_access3() nounwind ssp uwtable {
104entry:
105 %obj = alloca i64, align 8
106 %f = inttoptr i64 12297829382473034410 to i8*
107 %ret = call anyregcc i64 (i32, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i32 3, i32 12, i8* %f, i32 0, i64* %obj)
108 ret i64 %ret
109}
110
111; anyreg_test1
112; CHECK-NEXT: .long 4
113; CHECK-NEXT: .long L{{.*}}-_anyreg_test1
114; CHECK-NEXT: .short 0
115; 15 locations
116; CHECK-NEXT: .short 15
117; Loc 0: Register <-- this is the return register
118; CHECK-NEXT: .byte 1
119; CHECK-NEXT: .byte 0
120; CHECK-NEXT: .short {{[0-9]+}}
121; CHECK-NEXT: .long 0
122; Loc 1: Register
123; CHECK-NEXT: .byte 1
124; CHECK-NEXT: .byte 0
125; CHECK-NEXT: .short {{[0-9]+}}
126; CHECK-NEXT: .long 0
127; Loc 2: Register
128; CHECK-NEXT: .byte 1
129; CHECK-NEXT: .byte 0
130; CHECK-NEXT: .short {{[0-9]+}}
131; CHECK-NEXT: .long 0
132; Loc 3: Register
133; CHECK-NEXT: .byte 1
134; CHECK-NEXT: .byte 0
135; CHECK-NEXT: .short {{[0-9]+}}
136; CHECK-NEXT: .long 0
137; Loc 4: Register
138; CHECK-NEXT: .byte 1
139; CHECK-NEXT: .byte 0
140; CHECK-NEXT: .short {{[0-9]+}}
141; CHECK-NEXT: .long 0
142; Loc 5: Register
143; CHECK-NEXT: .byte 1
144; CHECK-NEXT: .byte 0
145; CHECK-NEXT: .short {{[0-9]+}}
146; CHECK-NEXT: .long 0
147; Loc 6: Register
148; CHECK-NEXT: .byte 1
149; CHECK-NEXT: .byte 0
150; CHECK-NEXT: .short {{[0-9]+}}
151; CHECK-NEXT: .long 0
152; Loc 7: Register
153; CHECK-NEXT: .byte 1
154; CHECK-NEXT: .byte 0
155; CHECK-NEXT: .short {{[0-9]+}}
156; CHECK-NEXT: .long 0
157; Loc 8: Register
158; CHECK-NEXT: .byte 1
159; CHECK-NEXT: .byte 0
160; CHECK-NEXT: .short {{[0-9]+}}
161; CHECK-NEXT: .long 0
162; Loc 9: Register
163; CHECK-NEXT: .byte 1
164; CHECK-NEXT: .byte 0
165; CHECK-NEXT: .short {{[0-9]+}}
166; CHECK-NEXT: .long 0
167; Loc 10: Register
168; CHECK-NEXT: .byte 1
169; CHECK-NEXT: .byte 0
170; CHECK-NEXT: .short {{[0-9]+}}
171; CHECK-NEXT: .long 0
172; Loc 11: Register
173; CHECK-NEXT: .byte 1
174; CHECK-NEXT: .byte 0
175; CHECK-NEXT: .short {{[0-9]+}}
176; CHECK-NEXT: .long 0
177; Loc 12: Register
178; CHECK-NEXT: .byte 1
179; CHECK-NEXT: .byte 0
180; CHECK-NEXT: .short {{[0-9]+}}
181; CHECK-NEXT: .long 0
182; Loc 13: Register
183; CHECK-NEXT: .byte 1
184; CHECK-NEXT: .byte 0
185; CHECK-NEXT: .short {{[0-9]+}}
186; CHECK-NEXT: .long 0
187; Loc 14: Register
188; CHECK-NEXT: .byte 1
189; CHECK-NEXT: .byte 0
190; CHECK-NEXT: .short {{[0-9]+}}
191; CHECK-NEXT: .long 0
192define i64 @anyreg_test1(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13, i8* %a14) nounwind ssp uwtable {
193entry:
194 %f = inttoptr i64 12297829382473034410 to i8*
195 %ret = call anyregcc i64 (i32, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i32 4, i32 12, i8* %f, i32 14, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13, i8* %a14)
196 ret i64 %ret
197}
198
199; anyreg_test2
200; CHECK-NEXT: .long 5
201; CHECK-NEXT: .long L{{.*}}-_anyreg_test2
202; CHECK-NEXT: .short 0
203; 15 locations
204; CHECK-NEXT: .short 15
205; Loc 0: Register <-- this is the return register
206; CHECK-NEXT: .byte 1
207; CHECK-NEXT: .byte 0
208; CHECK-NEXT: .short {{[0-9]+}}
209; CHECK-NEXT: .long 0
210; Loc 1: Register
211; CHECK-NEXT: .byte 1
212; CHECK-NEXT: .byte 0
213; CHECK-NEXT: .short {{[0-9]+}}
214; CHECK-NEXT: .long 0
215; Loc 2: Register
216; CHECK-NEXT: .byte 1
217; CHECK-NEXT: .byte 0
218; CHECK-NEXT: .short {{[0-9]+}}
219; CHECK-NEXT: .long 0
220; Loc 3: Register
221; CHECK-NEXT: .byte 1
222; CHECK-NEXT: .byte 0
223; CHECK-NEXT: .short {{[0-9]+}}
224; CHECK-NEXT: .long 0
225; Loc 4: Register
226; CHECK-NEXT: .byte 1
227; CHECK-NEXT: .byte 0
228; CHECK-NEXT: .short {{[0-9]+}}
229; CHECK-NEXT: .long 0
230; Loc 5: Register
231; CHECK-NEXT: .byte 1
232; CHECK-NEXT: .byte 0
233; CHECK-NEXT: .short {{[0-9]+}}
234; CHECK-NEXT: .long 0
235; Loc 6: Register
236; CHECK-NEXT: .byte 1
237; CHECK-NEXT: .byte 0
238; CHECK-NEXT: .short {{[0-9]+}}
239; CHECK-NEXT: .long 0
240; Loc 7: Register
241; CHECK-NEXT: .byte 1
242; CHECK-NEXT: .byte 0
243; CHECK-NEXT: .short {{[0-9]+}}
244; CHECK-NEXT: .long 0
245; Loc 8: Register
246; CHECK-NEXT: .byte 1
247; CHECK-NEXT: .byte 0
248; CHECK-NEXT: .short {{[0-9]+}}
249; CHECK-NEXT: .long 0
250; Loc 9: Register
251; CHECK-NEXT: .byte 1
252; CHECK-NEXT: .byte 0
253; CHECK-NEXT: .short {{[0-9]+}}
254; CHECK-NEXT: .long 0
255; Loc 10: Register
256; CHECK-NEXT: .byte 1
257; CHECK-NEXT: .byte 0
258; CHECK-NEXT: .short {{[0-9]+}}
259; CHECK-NEXT: .long 0
260; Loc 11: Register
261; CHECK-NEXT: .byte 1
262; CHECK-NEXT: .byte 0
263; CHECK-NEXT: .short {{[0-9]+}}
264; CHECK-NEXT: .long 0
265; Loc 12: Register
266; CHECK-NEXT: .byte 1
267; CHECK-NEXT: .byte 0
268; CHECK-NEXT: .short {{[0-9]+}}
269; CHECK-NEXT: .long 0
270; Loc 13: Register
271; CHECK-NEXT: .byte 1
272; CHECK-NEXT: .byte 0
273; CHECK-NEXT: .short {{[0-9]+}}
274; CHECK-NEXT: .long 0
275; Loc 14: Register
276; CHECK-NEXT: .byte 1
277; CHECK-NEXT: .byte 0
278; CHECK-NEXT: .short {{[0-9]+}}
279; CHECK-NEXT: .long 0
280define i64 @anyreg_test2(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13, i8* %a14) nounwind ssp uwtable {
281entry:
282 %f = inttoptr i64 12297829382473034410 to i8*
283 %ret = call anyregcc i64 (i32, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i32 5, i32 12, i8* %f, i32 8, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13, i8* %a14)
284 ret i64 %ret
285}
286
287declare void @llvm.experimental.patchpoint.void(i32, i32, i8*, i32, ...)
288declare i64 @llvm.experimental.patchpoint.i64(i32, i32, i8*, i32, ...)
289