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Matt Arsenault9aa45f02017-07-06 20:57:05 +00001//===--- AMDGPUMacroFusion.cpp - AMDGPU Macro Fusion ----------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file This file contains the AMDGPU implementation of the DAG scheduling
11/// mutation to pair instructions back to back.
12//
13//===----------------------------------------------------------------------===//
14
15#include "AMDGPUMacroFusion.h"
16#include "AMDGPUSubtarget.h"
17#include "SIInstrInfo.h"
18
19#include "llvm/CodeGen/MacroFusion.h"
20
21using namespace llvm;
22
23namespace {
24
25/// \brief Check if the instr pair, FirstMI and SecondMI, should be fused
26/// together. Given SecondMI, when FirstMI is unspecified, then check if
27/// SecondMI may be part of a fused pair at all.
28static bool shouldScheduleAdjacent(const TargetInstrInfo &TII_,
29 const TargetSubtargetInfo &TSI,
30 const MachineInstr *FirstMI,
31 const MachineInstr &SecondMI) {
32 const SIInstrInfo &TII = static_cast<const SIInstrInfo&>(TII_);
33
34 switch (SecondMI.getOpcode()) {
35 case AMDGPU::V_ADDC_U32_e64:
36 case AMDGPU::V_SUBB_U32_e64:
37 case AMDGPU::V_CNDMASK_B32_e64: {
38 // Try to cluster defs of condition registers to their uses. This improves
39 // the chance VCC will be available which will allow shrinking to VOP2
40 // encodings.
41 if (!FirstMI)
42 return true;
43
44 const MachineOperand *Src2 = TII.getNamedOperand(SecondMI,
45 AMDGPU::OpName::src2);
46 return FirstMI->definesRegister(Src2->getReg());
47 }
48 default:
49 return false;
50 }
51
52 return false;
53}
54
55} // end namespace
56
57
58namespace llvm {
59
60std::unique_ptr<ScheduleDAGMutation> createAMDGPUMacroFusionDAGMutation () {
61 return createMacroFusionDAGMutation(shouldScheduleAdjacent);
62}
63
64} // end namespace llvm