blob: 3c6c7e1d1b42641a013d3dc1abb360ad865a4ee1 [file] [log] [blame]
Matt Arsenault7596f132017-02-27 20:52:10 +00001; RUN: llc -march=amdgcn -mcpu=gfx901 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 -check-prefix=GCN %s
2
3; GCN-LABEL: {{^}}inline_asm_input_v2i16:
4; GCN: s_mov_b32 s{{[0-9]+}}, s{{[0-9]+}}
Matt Arsenault3dbeefa2017-03-21 21:39:51 +00005define amdgpu_kernel void @inline_asm_input_v2i16(i32 addrspace(1)* %out, <2 x i16> %in) #0 {
Matt Arsenault7596f132017-02-27 20:52:10 +00006entry:
7 %val = call i32 asm "s_mov_b32 $0, $1", "=r,r"(<2 x i16> %in) #0
8 store i32 %val, i32 addrspace(1)* %out
9 ret void
10}
11
12; GCN-LABEL: {{^}}inline_asm_input_v2f16:
13; GCN: s_mov_b32 s0, s{{[0-9]+}}
Matt Arsenault3dbeefa2017-03-21 21:39:51 +000014define amdgpu_kernel void @inline_asm_input_v2f16(i32 addrspace(1)* %out, <2 x half> %in) #0 {
Matt Arsenault7596f132017-02-27 20:52:10 +000015entry:
16 %val = call i32 asm "s_mov_b32 $0, $1", "=r,r"(<2 x half> %in) #0
17 store i32 %val, i32 addrspace(1)* %out
18 ret void
19}
20
21; GCN-LABEL: {{^}}inline_asm_output_v2i16:
22; GCN: s_mov_b32 s{{[0-9]+}}, s{{[0-9]+}}
Matt Arsenault3dbeefa2017-03-21 21:39:51 +000023define amdgpu_kernel void @inline_asm_output_v2i16(<2 x i16> addrspace(1)* %out, i32 %in) #0 {
Matt Arsenault7596f132017-02-27 20:52:10 +000024entry:
25 %val = call <2 x i16> asm "s_mov_b32 $0, $1", "=r,r"(i32 %in) #0
26 store <2 x i16> %val, <2 x i16> addrspace(1)* %out
27 ret void
28}
29
30; GCN-LABEL: {{^}}inline_asm_output_v2f16:
31; GCN: v_mov_b32 v{{[0-9]+}}, s{{[0-9]+}}
Matt Arsenault3dbeefa2017-03-21 21:39:51 +000032define amdgpu_kernel void @inline_asm_output_v2f16(<2 x half> addrspace(1)* %out, i32 %in) #0 {
Matt Arsenault7596f132017-02-27 20:52:10 +000033entry:
34 %val = call <2 x half> asm "v_mov_b32 $0, $1", "=v,r"(i32 %in) #0
35 store <2 x half> %val, <2 x half> addrspace(1)* %out
36 ret void
37}
38
39; GCN-LABEL: {{^}}inline_asm_packed_v2i16:
40; GCN: v_pk_add_u16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
Matt Arsenault3dbeefa2017-03-21 21:39:51 +000041define amdgpu_kernel void @inline_asm_packed_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> %in0, <2 x i16> %in1) #0 {
Matt Arsenault7596f132017-02-27 20:52:10 +000042entry:
43 %val = call <2 x i16> asm "v_pk_add_u16 $0, $1, $2", "=v,r,v"(<2 x i16> %in0, <2 x i16> %in1) #0
44 store <2 x i16> %val, <2 x i16> addrspace(1)* %out
45 ret void
46}
47
48; GCN-LABEL: {{^}}inline_asm_packed_v2f16:
49; GCN: v_pk_add_f16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
Matt Arsenault3dbeefa2017-03-21 21:39:51 +000050define amdgpu_kernel void @inline_asm_packed_v2f16(<2 x half> addrspace(1)* %out, <2 x half> %in0, <2 x half> %in1) #0 {
Matt Arsenault7596f132017-02-27 20:52:10 +000051entry:
52 %val = call <2 x half> asm "v_pk_add_f16 $0, $1, $2", "=v,r,v"(<2 x half> %in0, <2 x half> %in1) #0
53 store <2 x half> %val, <2 x half> addrspace(1)* %out
54 ret void
55}
56
57attributes #0 = { nounwind }