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gerrit-public.fairphone.software / toolchain / llvm-project / 9d42334e02c25ec77c4f465676806121b56e0764 / . / llvm / lib / Target / AArch64 / AArch64.td
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Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1//=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10//
11//===----------------------------------------------------------------------===//
12
13//===----------------------------------------------------------------------===//
Pankaj Godea67fea42016-06-15 17:24:52 +0000[diff] [blame]14// Target-independent interfaces which we are implementing.
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]15//===----------------------------------------------------------------------===//
16
17include "llvm/Target/Target.td"
18
19//===----------------------------------------------------------------------===//
20// AArch64 Subtarget features.
21//
22
23def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true",
24 "Enable ARMv8 FP">;
25
26def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
27 "Enable Advanced SIMD instructions", [FeatureFPARMv8]>;
28
29def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
James Molloy9d423342017-04-05 10:44:38 +0000[diff] [blame^]30 "Enable cryptographic instructions", [FeatureNEON]>;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]31
32def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
33 "Enable ARMv8 CRC-32 checksum instructions">;
34
Sjoerd Meijerd906bf12016-06-03 14:03:27 +0000[diff] [blame]35def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true",
36 "Enable ARMv8 Reliability, Availability and Serviceability Extensions">;
37
Joel Jones75818bc2016-11-30 22:25:24 +0000[diff] [blame]38def FeatureLSE : SubtargetFeature<"lse", "HasLSE", "true",
39 "Enable ARMv8.1 Large System Extension (LSE) atomic instructions">;
40
Chad Rosier58fb5f52017-01-16 16:28:43 +0000[diff] [blame]41def FeatureRDM : SubtargetFeature<"rdm", "HasRDM", "true",
42 "Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions">;
43
Ahmed Bougachab0ff6432015-09-01 16:23:45 +0000[diff] [blame]44def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
45 "Enable ARMv8 PMUv3 Performance Monitors extension">;
46
Oliver Stannard7cc0c4e2015-11-26 15:23:32 +0000[diff] [blame]47def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
48 "Full FP16", [FeatureFPARMv8]>;
49
Oliver Stannarda34e4702015-12-01 10:48:51 +0000[diff] [blame]50def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true",
51 "Enable Statistical Profiling extension">;
52
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]53/// Cyclone has register move instructions which are "free".
54def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
55 "Has zero-cycle register moves">;
56
57/// Cyclone has instructions which zero registers for "free".
58def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
59 "Has zero-cycle zeroing instructions">;
60
Akira Hatanakaf53b0402015-07-29 14:17:26 +0000[diff] [blame]61def FeatureStrictAlign : SubtargetFeature<"strict-align",
62 "StrictAlign", "true",
63 "Disallow all unaligned memory "
64 "access">;
65
Akira Hatanaka0d4c9ea2015-07-25 00:18:31 +0000[diff] [blame]66def FeatureReserveX18 : SubtargetFeature<"reserve-x18", "ReserveX18", "true",
67 "Reserve X18, making it unavailable "
68 "as a GPR">;
69
Matthias Braun651cff42016-06-02 18:03:53 +0000[diff] [blame]70def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true",
71 "Use alias analysis during codegen">;
72
73def FeatureBalanceFPOps : SubtargetFeature<"balance-fp-ops", "BalanceFPOps",
74 "true",
75 "balance mix of odd and even D-registers for fp multiply(-accumulate) ops">;
76
77def FeaturePredictableSelectIsExpensive : SubtargetFeature<
78 "predictable-select-expensive", "PredictableSelectIsExpensive", "true",
79 "Prefer likely predicted branches over selects">;
80
81def FeatureCustomCheapAsMoveHandling : SubtargetFeature<"custom-cheap-as-move",
82 "CustomAsCheapAsMove", "true",
83 "Use custom code for TargetInstrInfo::isAsCheapAsAMove()">;
84
85def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
86 "UsePostRAScheduler", "true", "Schedule again after register allocation">;
87
88def FeatureSlowMisaligned128Store : SubtargetFeature<"slow-misaligned-128store",
89 "Misaligned128StoreIsSlow", "true", "Misaligned 128 bit stores are slow">;
90
Evandro Menezes7784cac2017-01-24 17:34:31 +0000[diff] [blame]91def FeatureSlowPaired128 : SubtargetFeature<"slow-paired-128",
92 "Paired128IsSlow", "true", "Paired 128 bit loads and stores are slow">;
Matthias Braun651cff42016-06-02 18:03:53 +0000[diff] [blame]93
94def FeatureAlternateSExtLoadCVTF32Pattern : SubtargetFeature<
95 "alternate-sextload-cvt-f32-pattern", "UseAlternateSExtLoadCVTF32Pattern",
96 "true", "Use alternative pattern for sextload convert to f32">;
97
Matthias Braun46a52382016-10-04 19:28:21 +0000[diff] [blame]98def FeatureArithmeticBccFusion : SubtargetFeature<
99 "arith-bcc-fusion", "HasArithmeticBccFusion", "true",
100 "CPU fuses arithmetic+bcc operations">;
101
102def FeatureArithmeticCbzFusion : SubtargetFeature<
103 "arith-cbz-fusion", "HasArithmeticCbzFusion", "true",
104 "CPU fuses arithmetic + cbz/cbnz operations">;
Matthias Braun651cff42016-06-02 18:03:53 +0000[diff] [blame]105
Evandro Menezesb21fb292017-02-01 02:54:39 +0000[diff] [blame]106def FeatureFuseAES : SubtargetFeature<
107 "fuse-aes", "HasFuseAES", "true",
108 "CPU fuses AES crypto operations">;
109
Evandro Menezes455382e2017-02-01 02:54:42 +0000[diff] [blame]110def FeatureFuseLiterals : SubtargetFeature<
111 "fuse-literals", "HasFuseLiterals", "true",
112 "CPU fuses literal generation operations">;
113
Matthias Braun651cff42016-06-02 18:03:53 +0000[diff] [blame]114def FeatureDisableLatencySchedHeuristic : SubtargetFeature<
115 "disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true",
116 "Disable latency scheduling heuristic">;
117
Evandro Menezeseff2bd92016-10-24 16:14:58 +0000[diff] [blame]118def FeatureUseRSqrt : SubtargetFeature<
119 "use-reciprocal-square-root", "UseRSqrt", "true",
120 "Use the reciprocal square root approximation">;
Sanne Woudad4658ee2017-03-28 10:02:56 +0000[diff] [blame]121
122def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates",
123 "NegativeImmediates", "false",
124 "Convert immediates and instructions "
125 "to their negated or complemented "
126 "equivalent when the immediate does "
127 "not fit in the encoding.">;
128
Balaram Makam2aba753e2017-03-31 18:16:53 +0000[diff] [blame]129def FeatureLSLFast : SubtargetFeature<
130 "lsl-fast", "HasLSLFast", "true",
131 "CPU has a fastpath logical shift of up to 3 places">;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]132//===----------------------------------------------------------------------===//
Vladimir Sukharev439328e2015-04-01 14:49:29 +0000[diff] [blame]133// Architectures.
134//
135
136def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
Chad Rosier58fb5f52017-01-16 16:28:43 +0000[diff] [blame]137 "Support ARM v8.1a instructions", [FeatureCRC, FeatureLSE, FeatureRDM]>;
Vladimir Sukharev439328e2015-04-01 14:49:29 +0000[diff] [blame]138
Oliver Stannard7cc0c4e2015-11-26 15:23:32 +0000[diff] [blame]139def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
Sjoerd Meijerd906bf12016-06-03 14:03:27 +0000[diff] [blame]140 "Support ARM v8.2a instructions", [HasV8_1aOps, FeatureRAS]>;
Oliver Stannard7cc0c4e2015-11-26 15:23:32 +0000[diff] [blame]141
Vladimir Sukharev439328e2015-04-01 14:49:29 +0000[diff] [blame]142//===----------------------------------------------------------------------===//
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]143// Register File Description
144//===----------------------------------------------------------------------===//
145
146include "AArch64RegisterInfo.td"
Daniel Sandersd64d50242017-01-19 11:15:55 +0000[diff] [blame]147include "AArch64RegisterBanks.td"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]148include "AArch64CallingConvention.td"
149
150//===----------------------------------------------------------------------===//
151// Instruction Descriptions
152//===----------------------------------------------------------------------===//
153
154include "AArch64Schedule.td"
155include "AArch64InstrInfo.td"
156
157def AArch64InstrInfo : InstrInfo;
158
159//===----------------------------------------------------------------------===//
Tim Northovere6ae6762016-07-05 21:23:04 +0000[diff] [blame]160// Named operands for MRS/MSR/TLBI/...
161//===----------------------------------------------------------------------===//
162
163include "AArch64SystemOperands.td"
164
165//===----------------------------------------------------------------------===//
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]166// AArch64 Processors supported.
167//
168include "AArch64SchedA53.td"
Chad Rosier2205d4e2014-06-11 21:06:56 +0000[diff] [blame]169include "AArch64SchedA57.td"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]170include "AArch64SchedCyclone.td"
Chad Rosierd34c26e2016-11-29 20:00:27 +0000[diff] [blame]171include "AArch64SchedFalkor.td"
Chad Rosiercd2be7f2016-02-12 15:51:51 +0000[diff] [blame]172include "AArch64SchedKryo.td"
Chad Rosierd34c26e2016-11-29 20:00:27 +0000[diff] [blame]173include "AArch64SchedM1.td"
Joel Jonesab0f3b42017-02-17 18:34:24 +0000[diff] [blame]174include "AArch64SchedThunderX.td"
Joel Jones28520882017-03-07 19:42:40 +0000[diff] [blame]175include "AArch64SchedThunderX2T99.td"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]176
Christof Douma8b5dc2c2015-12-02 11:53:44 +0000[diff] [blame]177def ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",
Matthias Braun651cff42016-06-02 18:03:53 +0000[diff] [blame]178 "Cortex-A35 ARM processors", [
Christof Douma8b5dc2c2015-12-02 11:53:44 +0000[diff] [blame]179 FeatureCRC,
Matthias Braun651cff42016-06-02 18:03:53 +0000[diff] [blame]180 FeatureCrypto,
181 FeatureFPARMv8,
182 FeatureNEON,
183 FeaturePerfMon
184 ]>;
Christof Douma8b5dc2c2015-12-02 11:53:44 +0000[diff] [blame]185
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]186def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
Matthias Braun651cff42016-06-02 18:03:53 +0000[diff] [blame]187 "Cortex-A53 ARM processors", [
188 FeatureBalanceFPOps,
Ahmed Bougachab0ff6432015-09-01 16:23:45 +0000[diff] [blame]189 FeatureCRC,
Matthias Braun651cff42016-06-02 18:03:53 +0000[diff] [blame]190 FeatureCrypto,
191 FeatureCustomCheapAsMoveHandling,
192 FeatureFPARMv8,
193 FeatureNEON,
194 FeaturePerfMon,
195 FeaturePostRAScheduler,
196 FeatureUseAA
197 ]>;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]198
199def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
Matthias Braun651cff42016-06-02 18:03:53 +0000[diff] [blame]200 "Cortex-A57 ARM processors", [
201 FeatureBalanceFPOps,
Ahmed Bougachab0ff6432015-09-01 16:23:45 +0000[diff] [blame]202 FeatureCRC,
Matthias Braun651cff42016-06-02 18:03:53 +0000[diff] [blame]203 FeatureCrypto,
204 FeatureCustomCheapAsMoveHandling,
205 FeatureFPARMv8,
Evandro Menezesb21fb292017-02-01 02:54:39 +0000[diff] [blame]206 FeatureFuseAES,
Evandro Menezes455382e2017-02-01 02:54:42 +0000[diff] [blame]207 FeatureFuseLiterals,
Matthias Braun651cff42016-06-02 18:03:53 +0000[diff] [blame]208 FeatureNEON,
209 FeaturePerfMon,
210 FeaturePostRAScheduler,
211 FeaturePredictableSelectIsExpensive
212 ]>;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]213
Silviu Barangaaee40fc2016-06-21 15:53:54 +0000[diff] [blame]214def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
215 "Cortex-A72 ARM processors", [
216 FeatureCRC,
217 FeatureCrypto,
218 FeatureFPARMv8,
219 FeatureNEON,
220 FeaturePerfMon
221 ]>;
222
223def ProcA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73",
224 "Cortex-A73 ARM processors", [
225 FeatureCRC,
226 FeatureCrypto,
227 FeatureFPARMv8,
228 FeatureNEON,
229 FeaturePerfMon
230 ]>;
231
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]232def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone",
Matthias Braun651cff42016-06-02 18:03:53 +0000[diff] [blame]233 "Cyclone", [
234 FeatureAlternateSExtLoadCVTF32Pattern,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]235 FeatureCrypto,
Matthias Braun651cff42016-06-02 18:03:53 +0000[diff] [blame]236 FeatureDisableLatencySchedHeuristic,
237 FeatureFPARMv8,
Matthias Braun46a52382016-10-04 19:28:21 +0000[diff] [blame]238 FeatureArithmeticBccFusion,
239 FeatureArithmeticCbzFusion,
Matthias Braun651cff42016-06-02 18:03:53 +0000[diff] [blame]240 FeatureNEON,
Ahmed Bougachab0ff6432015-09-01 16:23:45 +0000[diff] [blame]241 FeaturePerfMon,
Matthias Braun651cff42016-06-02 18:03:53 +0000[diff] [blame]242 FeatureSlowMisaligned128Store,
243 FeatureZCRegMove,
244 FeatureZCZeroing
245 ]>;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]246
MinSeong Kima7385eb2016-01-05 12:51:59 +0000[diff] [blame]247def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1",
Evandro Menezesca837032016-10-26 22:06:20 +0000[diff] [blame]248 "Samsung Exynos-M1 processors",
Evandro Menezes7784cac2017-01-24 17:34:31 +0000[diff] [blame]249 [FeatureSlowPaired128,
Evandro Menezesca837032016-10-26 22:06:20 +0000[diff] [blame]250 FeatureCRC,
251 FeatureCrypto,
252 FeatureCustomCheapAsMoveHandling,
253 FeatureFPARMv8,
Evandro Menezesb21fb292017-02-01 02:54:39 +0000[diff] [blame]254 FeatureFuseAES,
Evandro Menezesca837032016-10-26 22:06:20 +0000[diff] [blame]255 FeatureNEON,
256 FeaturePerfMon,
257 FeaturePostRAScheduler,
Evandro Menezes1b48bac2016-12-16 00:18:00 +0000[diff] [blame]258 FeatureSlowMisaligned128Store,
Evandro Menezesca837032016-10-26 22:06:20 +0000[diff] [blame]259 FeatureUseRSqrt,
260 FeatureZCZeroing]>;
261
262def ProcExynosM2 : SubtargetFeature<"exynosm2", "ARMProcFamily", "ExynosM1",
Evandro Menezesaeec7802016-12-13 23:31:41 +0000[diff] [blame]263 "Samsung Exynos-M2/M3 processors",
Evandro Menezes7784cac2017-01-24 17:34:31 +0000[diff] [blame]264 [FeatureSlowPaired128,
Evandro Menezesca837032016-10-26 22:06:20 +0000[diff] [blame]265 FeatureCRC,
266 FeatureCrypto,
267 FeatureCustomCheapAsMoveHandling,
268 FeatureFPARMv8,
269 FeatureNEON,
270 FeaturePerfMon,
271 FeaturePostRAScheduler,
Evandro Menezes1b48bac2016-12-16 00:18:00 +0000[diff] [blame]272 FeatureSlowMisaligned128Store,
Evandro Menezesca837032016-10-26 22:06:20 +0000[diff] [blame]273 FeatureZCZeroing]>;
MinSeong Kima7385eb2016-01-05 12:51:59 +0000[diff] [blame]274
Chad Rosiercd2be7f2016-02-12 15:51:51 +0000[diff] [blame]275def ProcKryo : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo",
Matthias Braun651cff42016-06-02 18:03:53 +0000[diff] [blame]276 "Qualcomm Kryo processors", [
Chad Rosiercd2be7f2016-02-12 15:51:51 +0000[diff] [blame]277 FeatureCRC,
Matthias Braun651cff42016-06-02 18:03:53 +0000[diff] [blame]278 FeatureCrypto,
279 FeatureCustomCheapAsMoveHandling,
280 FeatureFPARMv8,
Matthias Braun651cff42016-06-02 18:03:53 +0000[diff] [blame]281 FeatureNEON,
282 FeaturePerfMon,
283 FeaturePostRAScheduler,
Haicheng Wu1e395742016-07-12 02:04:01 +0000[diff] [blame]284 FeaturePredictableSelectIsExpensive,
Balaram Makam2aba753e2017-03-31 18:16:53 +0000[diff] [blame]285 FeatureZCZeroing,
286 FeatureLSLFast
Matthias Braun651cff42016-06-02 18:03:53 +0000[diff] [blame]287 ]>;
Chad Rosiercd2be7f2016-02-12 15:51:51 +0000[diff] [blame]288
Chad Rosier201fc1e2016-11-15 21:34:12 +0000[diff] [blame]289def ProcFalkor : SubtargetFeature<"falkor", "ARMProcFamily", "Falkor",
290 "Qualcomm Falkor processors", [
291 FeatureCRC,
292 FeatureCrypto,
Chad Rosier63687e402017-01-04 21:26:23 +0000[diff] [blame]293 FeatureCustomCheapAsMoveHandling,
Chad Rosier201fc1e2016-11-15 21:34:12 +0000[diff] [blame]294 FeatureFPARMv8,
295 FeatureNEON,
Chad Rosier63687e402017-01-04 21:26:23 +0000[diff] [blame]296 FeaturePerfMon,
297 FeaturePostRAScheduler,
298 FeaturePredictableSelectIsExpensive,
Chad Rosier58fb5f52017-01-16 16:28:43 +0000[diff] [blame]299 FeatureRDM,
Balaram Makam2aba753e2017-03-31 18:16:53 +0000[diff] [blame]300 FeatureZCZeroing,
301 FeatureLSLFast
Chad Rosier201fc1e2016-11-15 21:34:12 +0000[diff] [blame]302 ]>;
303
Joel Jones28520882017-03-07 19:42:40 +0000[diff] [blame]304def ProcThunderX2T99 : SubtargetFeature<"thunderx2t99", "ARMProcFamily",
305 "ThunderX2T99",
306 "Cavium ThunderX2 processors", [
307 FeatureCRC,
308 FeatureCrypto,
309 FeatureFPARMv8,
310 FeatureArithmeticBccFusion,
311 FeatureNEON,
312 FeaturePostRAScheduler,
313 FeaturePredictableSelectIsExpensive,
314 FeatureLSE,
315 HasV8_1aOps]>;
Pankaj Gode0aab2e32016-06-20 11:13:31 +0000[diff] [blame]316
Joel Jonesab0f3b42017-02-17 18:34:24 +0000[diff] [blame]317def ProcThunderX : SubtargetFeature<"thunderx", "ARMProcFamily", "ThunderX",
318 "Cavium ThunderX processors", [
319 FeatureCRC,
320 FeatureCrypto,
321 FeatureFPARMv8,
322 FeaturePerfMon,
323 FeaturePostRAScheduler,
324 FeaturePredictableSelectIsExpensive,
325 FeatureNEON]>;
326
327def ProcThunderXT88 : SubtargetFeature<"thunderxt88", "ARMProcFamily",
328 "ThunderXT88",
329 "Cavium ThunderX processors", [
330 FeatureCRC,
331 FeatureCrypto,
332 FeatureFPARMv8,
333 FeaturePerfMon,
334 FeaturePostRAScheduler,
335 FeaturePredictableSelectIsExpensive,
336 FeatureNEON]>;
337
338def ProcThunderXT81 : SubtargetFeature<"thunderxt81", "ARMProcFamily",
339 "ThunderXT81",
340 "Cavium ThunderX processors", [
341 FeatureCRC,
342 FeatureCrypto,
343 FeatureFPARMv8,
344 FeaturePerfMon,
345 FeaturePostRAScheduler,
346 FeaturePredictableSelectIsExpensive,
347 FeatureNEON]>;
348
349def ProcThunderXT83 : SubtargetFeature<"thunderxt83", "ARMProcFamily",
350 "ThunderXT83",
351 "Cavium ThunderX processors", [
352 FeatureCRC,
353 FeatureCrypto,
354 FeatureFPARMv8,
355 FeaturePerfMon,
356 FeaturePostRAScheduler,
357 FeaturePredictableSelectIsExpensive,
358 FeatureNEON]>;
359
Matthias Braun651cff42016-06-02 18:03:53 +0000[diff] [blame]360def : ProcessorModel<"generic", NoSchedModel, [
361 FeatureCRC,
362 FeatureFPARMv8,
363 FeatureNEON,
364 FeaturePerfMon,
365 FeaturePostRAScheduler
366 ]>;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]367
Chad Rosier8e11fbd2017-01-24 18:08:10 +0000[diff] [blame]368// FIXME: Cortex-A35 is currently modeled as a Cortex-A53.
Christof Douma8b5dc2c2015-12-02 11:53:44 +0000[diff] [blame]369def : ProcessorModel<"cortex-a35", CortexA53Model, [ProcA35]>;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]370def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
Chad Rosier2205d4e2014-06-11 21:06:56 +0000[diff] [blame]371def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;
Chad Rosier8e11fbd2017-01-24 18:08:10 +0000[diff] [blame]372// FIXME: Cortex-A72 and Cortex-A73 are currently modeled as a Cortex-A57.
Silviu Barangaaee40fc2016-06-21 15:53:54 +0000[diff] [blame]373def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA72]>;
374def : ProcessorModel<"cortex-a73", CortexA57Model, [ProcA73]>;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]375def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>;
Evandro Menezesd761ca22016-02-06 00:01:41 +0000[diff] [blame]376def : ProcessorModel<"exynos-m1", ExynosM1Model, [ProcExynosM1]>;
Evandro Menezesca837032016-10-26 22:06:20 +0000[diff] [blame]377def : ProcessorModel<"exynos-m2", ExynosM1Model, [ProcExynosM2]>;
Evandro Menezesaeec7802016-12-13 23:31:41 +0000[diff] [blame]378def : ProcessorModel<"exynos-m3", ExynosM1Model, [ProcExynosM2]>;
Chad Rosierd34c26e2016-11-29 20:00:27 +0000[diff] [blame]379def : ProcessorModel<"falkor", FalkorModel, [ProcFalkor]>;
Chad Rosiercd2be7f2016-02-12 15:51:51 +0000[diff] [blame]380def : ProcessorModel<"kryo", KryoModel, [ProcKryo]>;
Joel Jonesab0f3b42017-02-17 18:34:24 +0000[diff] [blame]381// Cavium ThunderX/ThunderX T8X Processors
382def : ProcessorModel<"thunderx", ThunderXT8XModel, [ProcThunderX]>;
383def : ProcessorModel<"thunderxt88", ThunderXT8XModel, [ProcThunderXT88]>;
384def : ProcessorModel<"thunderxt81", ThunderXT8XModel, [ProcThunderXT81]>;
385def : ProcessorModel<"thunderxt83", ThunderXT8XModel, [ProcThunderXT83]>;
Joel Jones28520882017-03-07 19:42:40 +0000[diff] [blame]386// Cavium ThunderX2T9X Processors. Formerly Broadcom Vulcan.
387def : ProcessorModel<"thunderx2t99", ThunderX2T99Model, [ProcThunderX2T99]>;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]388
389//===----------------------------------------------------------------------===//
390// Assembly parser
391//===----------------------------------------------------------------------===//
392
393def GenericAsmParserVariant : AsmParserVariant {
394 int Variant = 0;
395 string Name = "generic";
Colin LeMahieu8a0453e2015-11-09 00:31:07 +0000[diff] [blame]396 string BreakCharacters = ".";
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]397}
398
399def AppleAsmParserVariant : AsmParserVariant {
400 int Variant = 1;
401 string Name = "apple-neon";
Colin LeMahieu8a0453e2015-11-09 00:31:07 +0000[diff] [blame]402 string BreakCharacters = ".";
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]403}
404
405//===----------------------------------------------------------------------===//
406// Assembly printer
407//===----------------------------------------------------------------------===//
408// AArch64 Uses the MC printer for asm output, so make sure the TableGen
409// AsmWriter bits get associated with the correct class.
410def GenericAsmWriter : AsmWriter {
411 string AsmWriterClassName = "InstPrinter";
Akira Hatanakab46d0232015-03-27 20:36:02 +0000[diff] [blame]412 int PassSubtarget = 1;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]413 int Variant = 0;
414 bit isMCAsmWriter = 1;
415}
416
417def AppleAsmWriter : AsmWriter {
418 let AsmWriterClassName = "AppleInstPrinter";
Akira Hatanakab46d0232015-03-27 20:36:02 +0000[diff] [blame]419 int PassSubtarget = 1;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]420 int Variant = 1;
421 int isMCAsmWriter = 1;
422}
423
424//===----------------------------------------------------------------------===//
425// Target Declaration
426//===----------------------------------------------------------------------===//
427
428def AArch64 : Target {
429 let InstructionSet = AArch64InstrInfo;
430 let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant];
431 let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter];
432}