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gerrit-public.fairphone.software / toolchain / llvm-project / a052037034df09335b964ef9dae91bb9b54c94fa / . / llvm / test / CodeGen / Mips / llvm-ir / select-int.ll
blob: 87f2ca4b8a1dab3fdb4acfcb2a1bdd39e1546e80 [file] [log] [blame]
Vasileios Kalintirisa0520372016-02-01 15:19:35 +0000[diff] [blame^]1; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
2; RUN: -check-prefix=ALL -check-prefix=M2 -check-prefix=M2-M3
3; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
4; RUN: -check-prefix=ALL -check-prefix=CMOV \
5; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R1
6; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
7; RUN: -check-prefix=ALL -check-prefix=CMOV \
8; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
9; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
10; RUN: -check-prefix=ALL -check-prefix=CMOV \
11; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
12; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
13; RUN: -check-prefix=ALL -check-prefix=CMOV \
14; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
15; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
16; RUN: -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-32
17; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
18; RUN: -check-prefix=ALL -check-prefix=M3 -check-prefix=M2-M3
19; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
20; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
21; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
22; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
23; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
24; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
25; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
26; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
27; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
28; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
29; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
30; RUN: -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-64
31
32define signext i1 @tst_select_i1_i1(i1 signext %s,
33 i1 signext %x, i1 signext %y) {
34entry:
35 ; ALL-LABEL: tst_select_i1_i1:
36
37 ; M2-M3: andi $[[T0:[0-9]+]], $4, 1
38 ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
39 ; M2-M3: nop
40 ; M2-M3: move $5, $6
41 ; M2-M3: $[[BB0]]:
42 ; M2-M3: jr $ra
43 ; M2-M3: move $2, $5
44
45 ; CMOV: andi $[[T0:[0-9]+]], $4, 1
46 ; CMOV: movn $6, $5, $[[T0]]
47 ; CMOV: move $2, $6
48
49 ; SEL: andi $[[T0:[0-9]+]], $4, 1
50 ; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
51 ; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]]
52 ; SEL: or $2, $[[T2]], $[[T1]]
53 %r = select i1 %s, i1 %x, i1 %y
54 ret i1 %r
55}
56
57define signext i8 @tst_select_i1_i8(i1 signext %s,
58 i8 signext %x, i8 signext %y) {
59entry:
60 ; ALL-LABEL: tst_select_i1_i8:
61
62 ; M2-M3: andi $[[T0:[0-9]+]], $4, 1
63 ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
64 ; M2-M3: nop
65 ; M2-M3: move $5, $6
66 ; M2-M3: $[[BB0]]:
67 ; M2-M3: jr $ra
68 ; M2-M3: move $2, $5
69
70 ; CMOV: andi $[[T0:[0-9]+]], $4, 1
71 ; CMOV: movn $6, $5, $[[T0]]
72 ; CMOV: move $2, $6
73
74 ; SEL: andi $[[T0:[0-9]+]], $4, 1
75 ; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
76 ; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]]
77 ; SEL: or $2, $[[T2]], $[[T1]]
78 %r = select i1 %s, i8 %x, i8 %y
79 ret i8 %r
80}
81
82define signext i32 @tst_select_i1_i32(i1 signext %s,
83 i32 signext %x, i32 signext %y) {
84entry:
85 ; ALL-LABEL: tst_select_i1_i32:
86
87 ; M2-M3: andi $[[T0:[0-9]+]], $4, 1
88 ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
89 ; M2-M3: nop
90 ; M2-M3: move $5, $6
91 ; M2-M3: $[[BB0]]:
92 ; M2-M3: jr $ra
93 ; M2-M3: move $2, $5
94
95 ; CMOV: andi $[[T0:[0-9]+]], $4, 1
96 ; CMOV: movn $6, $5, $[[T0]]
97 ; CMOV: move $2, $6
98
99 ; SEL: andi $[[T0:[0-9]+]], $4, 1
100 ; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
101 ; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]]
102 ; SEL: or $2, $[[T2]], $[[T1]]
103 %r = select i1 %s, i32 %x, i32 %y
104 ret i32 %r
105}
106
107define signext i64 @tst_select_i1_i64(i1 signext %s,
108 i64 signext %x, i64 signext %y) {
109entry:
110 ; ALL-LABEL: tst_select_i1_i64:
111
112 ; M2: andi $[[T0:[0-9]+]], $4, 1
113 ; M2: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
114 ; M2: nop
115 ; M2: lw $[[T1:[0-9]+]], 16($sp)
116 ; M2: $[[BB0]]:
117 ; FIXME: This branch is redundant
118 ; M2: bnez $[[T0]], $[[BB1:BB[0-9_]+]]
119 ; M2: nop
120 ; M2: lw $[[T2:[0-9]+]], 20($sp)
121 ; M2: $[[BB1]]:
122 ; M2: move $2, $[[T1]]
123 ; M2: jr $ra
124 ; M2: move $3, $[[T2]]
125
126 ; CMOV-32: andi $[[T0:[0-9]+]], $4, 1
127 ; CMOV-32: lw $2, 16($sp)
128 ; CMOV-32: movn $2, $6, $[[T0]]
129 ; CMOV-32: lw $3, 20($sp)
130 ; CMOV-32: movn $3, $7, $[[T0]]
131
132 ; SEL-32: andi $[[T0:[0-9]+]], $4, 1
133 ; SEL-32: selnez $[[T1:[0-9]+]], $6, $[[T0]]
134 ; SEL-32: lw $[[T2:[0-9]+]], 16($sp)
135 ; SEL-32: seleqz $[[T3:[0-9]+]], $[[T2]], $[[T0]]
136 ; SEL-32: or $2, $[[T1]], $[[T3]]
137 ; SEL-32: selnez $[[T4:[0-9]+]], $7, $[[T0]]
138 ; SEL-32: lw $[[T5:[0-9]+]], 20($sp)
139 ; SEL-32: seleqz $[[T6:[0-9]+]], $[[T5]], $[[T0]]
140 ; SEL-32: or $3, $[[T4]], $[[T6]]
141
142 ; M3: andi $[[T0:[0-9]+]], $4, 1
143 ; M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
144 ; M3: nop
145 ; M3: move $5, $6
146 ; M3: $[[BB0]]:
147 ; M3: jr $ra
148 ; M3: move $2, $5
149
150 ; CMOV-64: andi $[[T0:[0-9]+]], $4, 1
151 ; CMOV-64: movn $6, $5, $[[T0]]
152 ; CMOV-64: move $2, $6
153
154 ; SEL-64: andi $[[T0:[0-9]+]], $4, 1
155 ; FIXME: This shift is redundant
156 ; SEL-64: sll $[[T0]], $[[T0]], 0
157 ; SEL-64: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
158 ; SEL-64: selnez $[[T0]], $5, $[[T0]]
159 ; SEL-64: or $2, $[[T0]], $[[T1]]
160 %r = select i1 %s, i64 %x, i64 %y
161 ret i64 %r
162}